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Minutes of Weekly Meeting, 2008-10-06

Meeting called to order at 8:20am EDT

1. Roll Call

Brad Van Treuren
Adam Ley
Peter Horwood
Ian McIntosh
Carl Nielsen
Carl Walker
Eric Cormack
Heiko Ehrenberg
Tim Pender (joined at 8:43am EDT)

2. Review and approve 9/15/2008 minutes

minutes approved (moved by Ian, seconded by Eric)

3. Review old action items

4. Discussion Topics

    1. Status and review of white paper sections
      • Section 1: no changes / updates
      • Section 2: no changes / updates
      • Section 3: no additions / changes
      • Language Section: no changes / updates

 

    1. Poster Session Preparation/Suggestions
      • Brad and Ian worked on the layout of the poster;
      • overview slides for ITC Session 19 have been submitted;
      • brochure layout has been put on the website (http://www.sjtag.org/publications.html)

 

    1. Complete discussion of STAPL++
      (Gunnar's STAPL++ at http://files.sjtag.org/Ericsson-Nov2006/STAPL-Ideas.pdf; Brad's feedback to Gunnar was captured in http://files.sjtag.org/Ericsson-Nov2006/STAPLppFeedback.doc
      • [Brad] any further discussion on this?
      • [Ian] It may be helpful to clarify the differences in purpose of HSDL and STAPL++. HSDL and STAPL++ are serving very different applications. HSDL provides a description of the structure. STAPL++ shows how to package the vectors. It may provide a way to portability for pregenerated tests. There still needs to be a way of describing the structure of the circuit.
      • {Tim Pender joined}
      • [Brad] Re there any other comments on the STAPL++ discussion? The big thing was the concept of concurrency (last few slides in Gunnar's presentation).
      • [Ian] Concurrency may not be useful to everyone and may be questioned as to why we need it.
      • [Brad] For people with MBIST and LBIST, it is very important. No one thought when dot one was created with the RUNBIST instruction that there would be more than one MBIST or LBIST blocks in a design. That has changed and makes the RUNBIST useless.
      • [Ian] What is difficult is predicting what the requirements are going to be in the future.
      • [Carl W.] True, but we can use the past as an indicator so we don’t run into the same kind of scaling issues.

 

  1. Scope and Purpose Follow-up
    • submission of IEEE PAR postponed (see section 6 "other business" below)
    • [Brad] visit SJTAG Wiki, lower right has a link to scope and purpose
    • Voting on Scope and Purpose:
      • Approval of proposed Scope:
      • SCOPE

        This standard will develop a methodology for access to test, debug, instrument, configuration and/or programming, and emulation features (but not the features themselves) of devices via the IEEE 1149.1 Test Access Port (TAP) for the board and system (multiple board) domains.

        The elements for this methodology include a description language(s) describing the structure of how various standards (e.g., 1149.4, 1149.6, 1532, P1687, P1581) and other access mechanisms leverage the IEEE 1149.1 defined TAP interface in the system; a description of data representation formats for test vectors, diagnostic analysis, and data logging; and a software application programming interfaces (APIs) defining command primitives facilitating communications between functional command, control, and data modules of an SJTAG Test Manager application.
      • Heiko moved to accept, Ian seconded; unanimously accepted
         
      • Approval of proposed Purpose:
      • PURPOSE

        The purpose of the SJTAG standard is to provide an extension of the IEEE 1149.1 standard specifically aimed at enabling the configuration, control, management, and representation of the communications required at the hierarchical system and board levels to perform operations on the IEEE 1149.1 Test Access Port (TAP) of one or more devices or device cores, in a uniform and transportable way across all system modules.
      • Eric moved to accept, Heiko seconded; unanimously accepted
         
      • Additional descriptive text for "Need for the Project" section of the PAR:
        is currently no defined, independent standard for this test technology. Each vendor is free in the way of implementing test hardware and software functionality on their boards. Without an independent standard, testability at the system level is reduced or impossible making the test technology in the system less useful for users integrating designs from multiple sources limiting the ability to use the test technology in other facets of a product’s life cycle beyond manufacturing. In practice, the software used to perform test actions is written in an ad-hoc manner across the industry to access the IEEE 1149.1 features of the devices installed on the various boards of a system. Further, communications between remote and embedded hosts managing the tests applied to the system under test is non-existent or implemented using ad-hoc communications protocols.

5. Schedule next meeting

Monday, October 13th, 2008, 8:15am EDT
Wednesday, October 22nd, 2008, 8:15am EDT
Fringe Meeting at ITC Thursday, October 30th, 10:30-12:30 PDT.
Monday, November 10th, 2008, 8:15am EST
Monday, November 17th, 2008, 8:15am EST
Wednesday, November 26th, 2008, 8:15am EST

6. Any other business

7. Review new action items

none

8. Adjourn

meeting adjourned at 9:13 am EDT (moved by Ian, seconded by Eric)

Many thanks to Heiko in helping take notes for the 10/6 meeting.

Regards,
Brad