Minutes of Weekly Meeting, 2011-08-08

Call to Order: 11:05am

1. Roll Call

Carl Walker
Eric Cormack
Patrick Au
Heiko Ehrenberg
Peter Horwood
Brad Van Treuren
Adam Ley
Harrison Miles (joined 11:15)

Excused absences:
Ian McIntosh
Tim Pender

2. Review and approve previous minutes:

Approval of August 01 minutes (draft sent 1st August):

  • Corrections:
    • Heiko: "I we had P1687 …" -> "If we had P1687 …" (towards the end, in Harrison's comment)
    • Eric: I seem to remember a typo at the beginning of the notes, but I can't remember it now; I'll look again;
  • Mover: Eric
  • Second: Carl
  • minutes approved

3. Review old action items

  • Adam proposed we cover the following at the next meeting:
    • Establish consensus on goals and constraints
    • What are we trying to achieve?
    • What restrictions are we faced with?
  • All: do we feel SJTAG is requiring a new test language to obtain the information needed for diagnostics or is STAPL/SVF sufficient? see also Gunnar's presentation, in particular the new information he'd be looking for in a test language
  • Ian/Brad: Condense gateway comments and queries into a concise set of questions. - Ongoing
  • All: Forward text file to Ian containing keywords from review of meeting minutes. - Ongoing.
  • Carl/Brad: Get annotated keyword worksheets to Ian by Wednesday Close of Business. - Ongoing
  • All: Consider how a keyword can be used to define the chain configuration for a given test step, and what that keyword might be.

4. Discussion Topics

  1. Explore communication between a pair of devices
    - (device designators mentioned in the notes below refer to the diagrams in the slide set associated with this discussion)
    • Expand interconnect test diagram and description for Differential/SERDES:
      • differential signaling may "mask" some errors;
      • AC coupling capacitors could be discrete components, could be integrated in IC3 or IC4, or could be integrated (embedded) in the PCB substrate itself;
      • with AC coupled differential signaling, IC1 or IC2 need dot6 or IC3 and IC4 need self-test capability;
      • I/O configuration for IC1, IC2, IC3, and/or IC4 may be programmable and may need to be set up properly prior to any tests;
      • single ended receivers could add diagnostics / fault detection (differential receivers may miss some defects because of their inherent fault tolerance);
      • SERDES self-test would add fault coverage to boundary-scan connectivity test by testing link at functional speed;
    • Memory test:
      • memory may be non-boundary scan, may be IEEE 1149.1 compliant, or may be IEEE 1581-2011 compliant;
      • non-BScan memory: test based on read/write cycles; need access to all included signals; different categories of memories, with specific challenges (e.g. DDRx); Flash devices (and NAND in particular) have special requirements;
      • IEEE 1149.1 compliant memory: part of boundary-scan interconnect test; (note: some memories may provide "partial" [not fully compliant] IEEE 1149.1 implementations)
      • IEEE 1581: memory connectivity test becomes a simple logic cluster test;
      • any transparency between IC1 and IC5 (especially MUX) creates additional challenges for memory connectivity tests;
      • multiple memory devices may be "combined" in a wider data bus configuration (in one functional memory block, e.g. 4x memory with 8bit data bus each);
      • if IC1 doesn't provide boundary scan on one or multiple signals connected to the memory we rely on the creativity of the test engineer or additional (self-)test features provided by IC1;
      • 'smart' devices: if IC1 I/O impedance is programmable, its default may not be compatible with IC5 I/O impedance; recent complex devices introduce 'learning' of signal path properties after assembly on a board; electrical and functional (and signal) validation required; -> multi-step test process;
      • effective TCK rate (pattern reload rate); especially with (complex) dynamic memory we get to a point where boundary scan testing may not work reliably;
      • some boundary-scan devices (IC1) include memory BIST that can be used to test connections to external memory devices (IC5) at-speed; diagnostic capabilities depend on the BIST much more than on the tools used to apply the JTAG vectors;
      • IEEE P1687 may prove beneficial for the test of complex memory devices which can be considered "instruments" to target with P1687;

5. Key Takeaway for today's meeting

memory device with IEEE 1149.1 or IEEE 1581 simplifies memory connectivity test

6. Schedule next meeting

August 15, 2011, 11:00am EDT
Adam Ley and Brad Van Treuren may not be able to join;

7. Any other business


8. Review new action items


9. Adjourn

moved to adjourn by Peter, second by Eric.
meeting adjourned at 11:58am EDT