[SJTAG]

 The System JTAG Working Group

Minutes of Weekly Meeting, 2009-03-30

Meeting called to order at 10:35 AM EDT

1. Roll Call

Eric Cormack
Ian McIntosh
Adam Ley
Tim Pender
Carl Walker
Brad Van Treuren
Patrick Au

Excused:
Heiko Ehrenberg

2. Review and approve previous minutes:

3/23/2009 minutes

  • Draft circulated on 23rd March:
  • Corrections:
    • In section 3, delete two comments attributed to [Harrison] as these have been copied from the preceding week's notes.
  • Insufficient attendees to approve.

3. Review old action items

  • Adam proposed we cover the following at the next meeting:
    • Establish consensus on goals and constraints
    • What are we trying to achieve?
    • What restrictions are we faced with?
  • Establish whether TRST needs to be addressed as requirements in the ATCA specification if it is not going to be managed globally (All)
  • Adam review ATCA standard document for FRU's states
  • Patrick contact Cadence for EDA support person.
  • All to consider what data items are missing from Data Elements diagram
  • All: do we feel SJTAG is requiring a new test language to obtain the information needed for diagnostics or is STAPL/SVF sufficient?
    see also Gunnar's presentation, in particular the new information he'd be looking for in a test language (http://files.sjtag.org/Ericsson-Nov2006/STAPL-Ideas.pdf)
  • Adam: (continue) revise wording of section 5 - Ongoing
  • Carl W/Andrew: Set up conference call to organise review of Vol. 3 - Ongoing
  • Andrew: Make contact with VXI Consortium/Charles Greenberg. - Ongoing
  • Ian/Brad: Draft "straw man" Volume 4 for review - Ongoing
  • All: Review "Role of Languages" in White Paper Volume 4 - Ongoing
  • All: Consider structure/content of survey - Ongoing
  • Harrison: Virtual system exploiting Configuration/Tuning/Instrumentation and Root Cause Analysis/Failure Mode Analysis Use Cases. - Ongoing
  • Brad: Virtual system exploiting POST and BIST Use Cases. - Discussed in topic 4b.
  • Ian: Virtual system exploiting Environmental Stress Test Use Cases. - Ongoing

4. Discussion Topics

  1. Impact of 1149.7 on SJTAG
    • [Ian] I wanted to a have a discussion around 1149.7 and what it might mean for SJTAG. Tim raised a question on the use of bidirectional pins a while back and I believe there may be a number of aspects of dot 7 that could have a significant bearing on system JTAG architectures. Most articles I've seen in the trade journals don't seem to be very well informed.
    • [Patrick] I thought dot 7 had been dropped?
    • [Eric] You may be thinking of dot 5?
    • [Ian] Yes, dot 5 was trying to offer a system test bus.
    • [Adam] Dot 5 was dropped some time ago. The dot 7 activity started in 2006 and is now at ballot. Dot 7 is not a system test bus.
    • [Eric] One thing I see is the classes, T0 through to T5: Do we have to spread any support across all classes or could we simply support only T0?
    • [Adam] Dot7 is a specification for a chip level access port. It really only affects the test access port - how you access the test infrastructure on the chip. Each device vendor is free to choose which class his device will support; hopefully there enough options that they will find at least one class they are happy with. We will see chips that have a 2 pin interface where we would like a 4 pin interface, but we will have to live with it. A key aspect of dot7 is that there should be a fully compliant dot 1 boundary-scan architecture supported at the chip level.
    • [Ian] I thought that devices default to T0 and then you can transition to the next level classes, but all devices support T0.
    • [Adam] Each higher level class presumes all the capabilities of the lower level classes. One case of exception is where lower levels require 4 wire interfaces. Once you get to T4 and T5, you can support a 2 wire interface.
    • [Ian] OK, but if you have 4 or 5 wires for T0, how are you saving pins in T4 and T5?
    • [Adam] All the signalling to transition through the classes requires only the TCKC and TMSC, so you are only using the two pins that you would need for T4. TDI and TDO are only needed for scan operations.
    • [Adam] Stepping through the classes uses Zero Bit DR Scans (ZBS). A ZBS starts with Capture-DR and ends up in Update-DR without passing through Shift-DR. Counting ZBSs moves the device through the control levels. Once you are at control Level 2, which is the minimal command state, the dot 7 control logic is used to decode additional command words. Counting TCKCs in Shift-DR will produce a 5-bit word, and these can be concatenated to produce a longer command word.
    • [Ian] Where do we feel the uptake is? Is this more oriented towards wireless, small form factor applications or is it more for the emulation features?
    • [Patrick] It must be for the latter case.
    • [Adam] This is certainly driven from the emulation perspective. If your chip has no obvious processing capability then dot 7 probably isn't for you, but most complex chips have a processor in some form or other.
    • [Adam] Some chips have multiple emulation ports, but you want to share the emulation pins. You get some device stacks that might be a DSP, a microprocessor and a NAND Flash with it's controller, all with emulation ports. Bringing out 6 or 7 pins for each on the package isn't that attractive.
    • [Adam] How dot 7 gets brought up to the system level hasn't been thought about too much, but a bit more than dot 1 ever did. There is a fairly small section that discusses considerations for large system applications.
    • [Adam] I can extract that and circulate it for your comments. {ACTION}
    • [Ian] Thanks Adam, I think that'd be helpful.
    • [Tim] If you have several dot 7 devices, is there a way defined for you to connect these together?
    • [Ian] There a few ways to connect devices, like the Star topography... Sorry, Adam I should let you speak.
    • [Adam] If you have T4 or T5 devices supporting only 2 pins then these are called T4 Narrow or T5 Narrow, and you can only use the star topology connection. In other classes, the star connection implies that devices share TCKC and TMSC, but once a chip is addressed then it receives on TDI and sends on TDO.
    • [Tim] So if you have dot 7 chips but a traditional controller, do you need an adapter?
    • [Adam] You will need an adapter on the debug test system (DTS). Asset Intertech are working on that, and guess most other JTAG vendors will too.
    • [Adam] From last week's notes, I gather some people are interested in using the 2-wires in the backplane?
    • [Brad] Yes, I've had enquiries on that.
    • [Adam] The key challenge is that for 2 wires TMSC is bidirectional. You'll have cases where the driver is in the middle of a long and highly loaded backplane; Master and Slave may be close together or separated, but remember that both have to drive.
    • [Brad] The people who are asking say that they are already managing bidirectional signals and believe they can just use the same techniques here.
    • [Adam] Well, it could be very attractive for them if they can do that.
    • [Adam] When you have dot 1 devices along with dot 7 devices, you can provide an adaption to drive a dot 1 target, in fact the standard shows this adaption.
    • [Brad] So you could address a dot 1 chain using the dot 7 medium.
    • [Brad] Are there multiple addressing schemes. For example addresses for boards? How do you manage synchronisation across boards?
    • [Adam] How is that any different from dot 1?
    • [Brad] Well, there is a single addressing scheme there.
    • [Tim] How is addressing handled? If I have a quad core processor, how do I know which core I'm accessing?
    • [Adam] Addressing cores isn't a dot 7 function, addressing a chip is. Each chip has a Controller ID (CID) that is based on its device ID code and its node ID. The topology is enumerated and each chip produces a "serial number". You can have Long Form Addressing (36-bit word) or you can assign short addresses for some things.
    • [Adam] You can get duplicate CIDs if you have multiple discrete topologies, but you differentiate these as one will be on TAP 1, the other on TAP 2.
    • [Adam] From what I've seen, many chips will use some pins at power-on or reset to define the node ID, after which those pins can be repurposed.
    • [Brad] Something like the command word on Power PC?
    • [Adam] I'm not too familiar with Power PC, but I believe so.
    • [Brad] In 6.3.3.3, it talks about local and global registers; can you talk about that?
    • [Adam] Certain commands, like Store Format, have a global effect across all dot 7 devices; commands that affect the behaviour of the whole branch.
    • [Brad] If you've addressed a particular chip, how does it know to treat a command as global?
    • [Adam] It's a built-in effect of the global command. All chips see all commands.
    • [Brad] So the controller runs all the time, but only reacts if its address has been selected.

  2. 2009 Survey
    • [Ian] Brad has added a post to the forums on POST (http://forums.sjtag.org/viewtopic.php?f=14&t=32).
    • [Brad] Yes, I tried to write up a description, following the model you set with EST. I have some more to add, including some diagrams, but it's not ready yet.
    • [Ian] Well there's quite a bit there to read over now, and maybe we'll have something from Harrison for next week, too.
    • [Ian] One thing I need to do is to to go back over my text and see what survey questions can be distilled from that.
    • [Brad] And there's a list of thirty or so questions further up in the POST discussion that could still be useful.

5. Schedule next meeting

Schedule for April 2009:
Monday Apr. 6, 2009, 10:30 AM EDT
Monday Apr. 13, 2009, 10:30 AM EDT
Monday Apr. 20, 2009, 10:30 AM EDT
Monday Apr. 27, 2009, 10:30 AM EDT

6. Any other business

  • [Ian] I had forgotten about the Newsletter this month, and quickly put one together over the weekend. There's not very much in it. I see that font looks odd on one of the headings. I'll fix that.
  • [Brad] Maybe we can add something on the Virtual Systems. It'd help show that the Use Cases are still active topics, not something we've finished with and put aside. I think some people will be interested in that.
  • [Ian] OK, I'll add a section on that, then re-circulate a draft for e-mail approval. {ACTION}

7. Review new action items

  • Adam: Circulate section of 1149.7 draft which considers system level behaviour.
  • Ian: Add section to Newsletter on Virtual Systems activity, and re- circulate.

8. Adjourn

Moved to adjourn at 11:30 AM EDT by Eric, seconded by Patrick.

Thanks to Brad for supplying additional notes.

Respectfully submitted,
Ian McIntosh

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