Minutes of Weekly Meeting, 2010-03-29
Meeting called to order at 10:37 AM EST
1. Roll Call
Adam Ley
Brad Van Treuren
Heiko Ehrenberg
Ian McIntosh
Patrick Au (joined 11:01)
Excused:
Tim Pender
Peter Horwood
Carl Walker
Eric Cormack
Michele Portolan
2. Review and approve previous minutes:
03/22/2010 minutes:
- Draft circulated on 22nd March:
- No corrections noted.
- Insufficient attendance to approve these minutes at this time.
3. Review old action items
- Adam proposed we cover the following at the next meeting:
- Establish consensus on goals and constraints
- What are we trying to achieve?
- What restrictions are we faced with?
- Establish whether TRST needs to be addressed as requirements in the ATCA
specification if it is not going to be managed globally (All)
- Adam review ATCA standard document for FRU's states
- All to consider what data items are missing from Data Elements diagram
- All: do we feel SJTAG is requiring a new test language to obtain the
information needed for diagnostics or is STAPL/SVF sufficient?
see also Gunnar's presentation, in particular the new information he'd be
looking for in a test language
(http://files.sjtag.org/Ericsson-Nov2006/STAPL-Ideas.pdf)
- Ian/Brad: Draft "straw man" Volume 4 for review - Ongoing
- All: Review "Role of Languages" in White Paper Volume 4 - Ongoing
- All: Review 'straw man' virtual systems and notes on forums:
http://forums.sjtag.org/viewtopic.php?f=29&t=109. - Ongoing
- All: Add to, or comment on, the bullet point list of architecture drivers. -
Ongoing.
- All: Provide forum comment on the graphics used during the meeting; suggest
"building blocks" that may be used in future:
http://forums.sjtag.org/viewtopic.php?f=29&p=257#p257 - Ongoing.
- Heiko: create forum entries for what we have so far for further discussions /
details; send out an email with links to these new forum topics. - COMPLETE
- ALL: review / comment in preparation for upcoming meetings. - Ongoing
- Ian: Draft a generic system diagram for discussion next week. - COMPLETE.
- Ian: Make update of diagram discussed today available through the website. -
COMPLETE
- It was agreed to close out the actions relating to ATCA as JTAG has not been
adopted as part of that standard.
4. Discussion Topics
- White Paper Volume 3 Review - Discussion of sample system diagram
- [Ian] As actioned last week, I posted the slides from last week on the forum
after adding a new introductory diagram.
- {Forum post shared}
- [Ian] In the new diagram I've tried to capture what Brad was describing, as
a prefaces to my original slide. Is this the kind of thing you envisaged,
Brad?
- [Brad] Yes, I think it's difficult to format it any other way without
over-whelming the reader.
- [Ian] I am a bit wary of coming over too patronising to the more experienced
reader though. It's maybe something that come from the survey; that showed
that many of our current audience have a fair degree of sophistication. At
the same time we do need to lead the novice through, and that's maybe more
important.
- [Ian] I had thought of breaking the backplane up to show that each case was
a separate "system". I was being a bit economical with my time when I drew
that up.
- [Brad] Maybe the backplane is unnecessary there and we should be talking
about the TAP interface at the board edge.
- [Ian] I was reflecting the discussion that we should show that the board
TAP is simply extended through the backplane. But maybe we should start with
the very basic single chain board test scenario that every should be able to
relate to.
- [Brad] Yeah, then we have a natural progression moving on from there.
- [Ian] OK so we can rework that a little. Brad, you've sent me some other
slides?
- [Brad] Yes, it's something I'd been working on around the "primitives"; I
wondered if I'd be able share this.
- {PowerPoint slides shared}
- [Brad] These were as far as I'd got; I had hoped to get a bit more done
before the meeting.
- {Slide 3}
- [Brad] This starts with the scan cell as the basic I/O primitive. This is a
graphical representation of a typical scan cell, using the type of diagram
from 1149.1. The main thing was to show that it captures parallel data and
can substitute parallel data as the output. I then show the simplified
representation of the cell.
- {Slide 4}
- [Brad] Then there's the progression to the Register; an ordered collection
of scan cells that can be observed or modified within a single, functional
operation, and may be grouped with other scan registers.
- {Slide 5}
- [Brad] The scan chain - I wondered about calling it a scan segment - has
registers connected in an ordered fashion. Registers can have functional
operations that are disjoint from each other, e.g BYPASS or EXTEST.
- [Ian] At this point we seem to have something that equates to the simplest
of the board diagrams from my slides.
- [Brad] Well, yes but I still want to explain that the chain may change over
time as you make register selections - it's part of what is already there
even if people don't realise it. And then you can aggregate, make a
composite of scan chains.
- {Slide 7}
- [Brad] This is using the diagrams from 1149.1 to show the TAP Controller and
using register selection; a data register or an instruction register.
- {Patrick joined}
- {Slid 8}
- [Brad] This is just talking about the state machine. I prefer this to the
one in 1149.1 because it has the TMS values on it so maybe even people that
don't know state diagrams can follow this one.
- [Ian] It's the version I use.
- [Brad] I was working this way to try to show that as we go higher up we can
collapse these when we describe what a board is. That way people realise
that these are not really "black boxes" but "white boxes".
- [Brad] The difficulty I'm having is at what point do we introduce concept of
chain selection.
- [Ian] That was something that I was trying to stay away from in my original
diagram, because that was too much detail at that stage. But maybe that's
the next step on from my diagrams?
- [Brad] Possibly it is.
- [Ian] We don't want to end up with too much detail. I think that was a
problem in the original white paper: The diagrams tended show so many
different features on the boards that it wasn't clear what was relevant.
- [Brad] Detail and choices add up to frustration for the reader.
- [Ian] Do the others think this is useful, the right way to proceed?
- [Adam] It looks like this is coming along nicely.
- [Heiko] How much more detail from the dot 1 standard would you go into?
- [Brad] No more than you see, just showing that they're already doing
selection, but in a less obvious way.
- [Heiko] Even for people used to boundary scan, it's useful to use these
simple blocks.
- [Ian] Did you have plans to go beyond these Brad?
- [Brad] I ran out of time, but yes.
- [Ian] I see these running parallel to some of the elements in my diagrams.
Is there a point where we can merge the slides?
- [Brad] I wanted to go into some of the concepts of HSDL: The external paths,
static paths and dynamic paths. The external and static paths are basically
a representation of what is on boards. I do like what HSDL does in some
areas, like external paths that cannot be defined up-front.
- [Brad] The dot 1 controller means that static paths are not really static;
maybe static external to the devices.
- [Ian] I guess we're building a PowerPoint tutorial here. I like that,
because I think that once we build up the slide set into something we're
happy with, then how we transcribe that into a wiki document will probably
describe itself.
- [Brad] It'll help us to prepare something that we can present to the rest of
the group. The questions we get there will then help us to answer the
questions we'd get from readers.
5. Schedule next meeting
There is no meeting on April 5th.
Schedule for April 2010:
Monday April 12, 2010, 10:30 AM EDT
Monday April 19, 2010, 10:30 AM EDT
Monday April 26, 2010, 10:30 AM EDT
Eric will likely miss all meetings in April.
6. Any other business
None.
7. Review new action items
None.
8. Adjourn
Brad moved to adjourn at 11:24 AM EST, seconded by Patrick.
Respectfully submitted,
Ian McIntosh