Minutes of Weekly Meeting, 2017-05-15

Meeting called to order: 11:13 AM EDT

1. Roll Call

Ian McIntosh
Eric Cormack
Heiko Ehrenberg
Brad Van Treuren
Brian Erickson
Peter Horwood (joined 11:19)

By Proxy:
---

Excused:
Bill Eklow
Carl Walker


2. Review and approve previous minutes:

  • Approval of May 08 minutes (updated draft circulated on 05/10/2017)
    • Brian moved to approve, seconded by Brad. No objections or abstentions.

3. Review old action items

  • All: do we feel SJTAG is requiring a new test language to obtain the information needed for diagnostics or is STAPL/SVF sufficient? See also Gunnar's presentation, in particular the new information he'd be looking for in a test language (http://files.sjtag.org/Ericsson-Nov2006/STAPL-Ideas.pdf)
  • Ian: Add the previously discussed lists to the 'master' template. Ongoing.
    • Some sections need further expansion that may take time to develop.

4. Reminders

  • Consider Adam's three points (from the action from the first weekly meeting) and suggest what is preventing us from answering those questions:
    • Establish consensus on goals and constraints
    • What are we trying to achieve?
    • What restrictions are we faced with?
  • Forum thread for discussion: http://forums.sjtag.org/viewtopic.php?f=3&t=172
  • Possible invitation for Al Crouch to talk about Parallel SIBs.
  • Python Netlists (SKIDL) suggested by Brad for discussion.

5. Discussion Topics

a. Building Blocks - Use Case of a simple Interconnect Test - Continued, Implications for tooling.

  • Return to the topic originally scheduled for the previous meeting.
  • {Brad shared the DSL code samples prepared during the May 1 meeting}
  • Brad recalled one question being whether the JTAG example could be made to look more like the I2C and SPI examples.  Ian noted that this might mean time separating the input and output data, thereby removing some of the "efficiency" of the test data streams. Brad mentioned that Jeff Rearick had argued (in the 1687.1 meeting) that it was possible using iWrite(), iRead() and iApply(), so Brad proposed trying to re-write the JTAG example in a PDL-like form.
  • {1687 standard shared, as reference for syntax}
  • Ian agreed that the JTAG format made it difficult to follow what was input and what was output; it should be clearer in PDL. Heiko suggested that using 'H' and 'L' instead of '1' and '0' for driven bits might help readability. Brad edited the existing code samples accordingly, using 'D' for driven Don't Care bits.
  • Brad noted that the 1687 standard simply sees the writing to registers or reading from registers, without any bias to whether the interface is serial or parallel - the retargeting at iApply() will deal with that.
  • Brad started composing PDL statements to represent the JTAG vectors. Ian questioned if this was correct as the iRead() was using the expected result data, not the data that would be shifted out during the iWrite(). Brad said this had been part of his question to Jeff, but was assured that it was the retargetter's responsibility to handle this: This is the model of the registers that the resolver has to fix.
  • Ian was unconvinced, but in any case noted that in a practical case there could be numerous iRead() and iWrite() statements before the iApply() statement and these could be in any order and the retargetter would need to resolve the most effective way of applying them in a single step. Brad agreed and observed that this probably meant that it wasn't enough to have groups of iWrite(), iRead() and iApply() (in that order), there likely needed to be an iApply() after the iWrite().  Without that, Brad felt that the board netlist would need to be represented in ICL in order to determine the dependencies.
  • Brad will send our DSL and diagrams to Jeff and Martin for comment on our observations {ACTION}.
  • Ian felt that the resultant PDL we had arrived at seemed clumsy and probably inefficient compared to the "pure JTAG" version. Brad agreed that it was much larger in terms of code size.
  • The updated DSL code is here: http://files.sjtag.org/Brad/Example%20DSL%20of%20Models_20170515.txt.

6. Topic for next meeting

  • Building Blocks - Use Case of a simple Interconnect Test - continuation.
    • May have feedback on PDL enquiry.

7. Key Takeaway for today's meeting

  • Order of statements may depend on whether the interface is serial or parallel.

8. Glossary terms from this meeting

  • Carried over:
    • Definition of "interchangeability" required.
    • 'Instance' (or a more specific version of the term) may require definition in future.
    • 'Master through Slave Mode'
    • 'Master to Master Mode'
    • Need a refined definition of "system" for the purposes of the PAR.
    • 'Priority' - may relate to 'frequency' and 'urgency' in distinct definitions.

9. Schedule next meeting

  • Next meeting May 22.
  • May schedule:
    • May 29 is Memorial Day in the US and a UK holiday, Ian will be out, so no meeting that week.
    • Heiko will be out June 5.

10. Any other business

  • Ian hopes Michele will be able to provide a fuller report on the TESTA tutorial in due course.

11. Review new action items

  • Brad: Send diagrams and DSL to Jeff Rearick and Martin Keim for comment.

12. Adjourn

  • Peter moved to adjourn, seconded by Brian.
  • Meeting adjourned at 12:02 PM EDT

Respectfully submitted,
Ian McIntosh