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<2009 Survey, Sections 1, 2 User Survey 2009 Results 2009 Survey, Section 4>

Section 3 - Some general questions about your use of JTAG...


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3.1 - How would you describe your current usage of JTAG for board tests?

  1. I use JTAG tests developed by someone else
  2. I regularly prepare JTAG tests
  3. I sometimes prepare JTAG tests
  4. I have used JTAG in the past
  5. I have not yet used JTAG

The majority of respondents are actively involved in the preparation of board level tests using JTAG, with half being regularly involved in that activity. Only 5% are not active users of JTAG.

 

This gives some confidence that the people participating in the survey are competent to comment on the general application of JTAG, and may be expected to be aware of some of the issues that may be experienced when moving to system level applications.

 


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3.2 - Have you used JTAG for board level or system level applications?

For the purposes of this question, 'system' includes any multi-board assembly.

  1. Only for board level applications
  2. Mainly for board level applications
  3. Mainly for system level applications
  4. Only for system level applications
  5. Both board and system level applications

This is quite encouraging, as a little over half are acknowledging some experience of using JTAG at system level. So, building on the responses from Q3.1, we can now see a picture where a substantial portion of the participants have experience of both the board level and system level application of JTAG.

 


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3.3 - Which of these JTAG related standards and terms are you aware of?

Mark all that apply and note that some of these terms are equivalent.

  1. IEEE Std 1149.1
  2. IEEE Std 1149.4
  3. IEEE Std 1149.6
  4. IEEE Std 1149.7
  5. IEEE Std 1532
  6. IEEE P1581
  7. IEEE P1687
  8. SJTAG
  9. IJTAG
  10. CJTAG

This question was to establish whether people were following developments in JTAG and related fields across a spectrum of application areas or were more focussed on specific areas. Some of the terms used were equivalents (e.g. IJTAG and IEEE P1687) since it was felt that some people may recognize one designation but not the other.

While it is encouraging that most people recognized most terms, it is still notable that almost everyone who responded to this question was not aware of one or more of these standards or initiatives. We have to allow for some of these to be simply omissions, and indeed one responded professed to be unaware of IEEE Std 1149.1, which we have to assume to be an error, given that person's other responses to this questionnaire!

In fact, this may be highlighting a broader issue, as the aswers provided in Sections 1 and 2 demonstrate that we are not dealing with unsophisticated users in this survey. The fact that some major initiatives are seemingly unknown to some of these users may indicate that the TTTC standards activities as a whole are not achieving sufficient visibility.

 


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3.4 - Typically, how do you control your JTAG tests?

  1. Controlled entirely external to the unit under test via 5 wire TAP
  2. Controlled external to the unit under test via high level bus
  3. Controlled entirely within the unit under test (fully embedded)
  4. A mixture of the above

Perhaps this question could have benefitted from a few more options to properly tease out the detail. What we can determine is that majority of users are still reliant on using external controllers for JTAG applications. While a sizeable proportion are using a mixture of control options, we cannot determine from this which proportion are mixing external control with embedded control, etc., but clearly we have to be aware that within any given design there is likely to be a need to support multiple control interfaces.

Within the group using a mixture of control options, there will be those who employ fully embedded control. What we don't see, rightly, are people claiming to use only embedded control, as this would be highly impractical.

 


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Other responses:

  • Caslan (Goepel proprietary), Goepel Cascon, VHDL, when verifieing DFT structures at silicon
  • CASLAN, compiled CASLAN object code, bsdl, VB

3.5 - The languages I use for my JTAG Applications are:

  1. SVF
  2. STAPL
  3. C/C++
  4. C#
  5. Ruby
  6. Python
  7. TCL
  8. Perl
  9. Java
  10. Whatever languages my tools use

We attempted to find out if there were languages that were preferred in preparing and executing JTAG applications. We could have split this down into languages used when preparing a test, when executing a test, when programming a board, etc., but chose to leave this question quite open ended in order to allow people to determine their own interpretation of what was an applicable language here.

Not surprisingly, the well established SVF and STAPL languages are well represented, as are the tool vendors own choices (which may or may not be proprietary). Of the more conventional programming languages mentioned C/C++ appears as the most popular, and this may be driven by the choice of ATE control software, such as National Instrument's LabWindows.

 


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"Why not" responses:

  • Should be open for dif. languages for people with different skills
  • It depends on what the language is expected to do: If it is a way to detail the UUT then probably. If it is to control and sequence tests, then probably not.
  • I feel there needs to be standard description languages to describe the circuit under test. There needs to be a standard application programming interface (API) callable by the end user's lanugage of choice perhaps implementable using the SWIG tool

3.6 - Do you feel SJTAG needs a standard language for JTAG in a system?

  1. Yes
  2. No

The vast majority agree that a standard language is needed for System JTAG, but the comments show that people are seeing different uses for a language, which is perhaps to be expected given the comments made for Q3.5. The "Why not" responses are capturing the different levels involved and so it is still encouraging that people feel that there is a prospect for some standardization.

 


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3.7 - I am able to describe my circuit elements/modules (e.g., mezzanines, boards, backplanes, system) to my test tools using:

(check all that apply)

  1. C/ATLAS
  2. VHDL
  3. Verilog
  4. SystemC
  5. HSDL
  6. Tool provided design language
  7. Proprietary design language
  8. A collection of CAD output files
  9. A collection of proprietary user defined model files
  10. A standard description file other than BSDL
  11. No means to describe the circuit to the tooling are possible

From the results for this question and Q3.8 there were two items in particular that attracted our attention: The first item of interest, relating mainly to this question, was the number of respondents citing VHDL. While many current board designs may be simplisticly described as an FPGA with some I/O buffering, hence the VHDL for the FPGA describes the function of the board, the perception from the P1687 group was that VHDL may be overkill for embedded instrumentation. If VHDL is a viable description language for SJTAG then this may be an area of divergence with IJTAG.

 


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3.8 - I am able to describe the assembly of modules within my system using:

(check all that apply)

  1. C/ATLAS
  2. VHDL
  3. Verilog
  4. SystemC
  5. HSDL
  6. Tool provided assembly description language
  7. Proprietary assembly description language
  8. A collection of CAD output files
  9. User generated description file(s)
  10. A standard description file(s) other than BSDL
  11. Only merging/flattening netlists techniques
  12. No means to describe the assembly to the tooling are possible

Following on from Q3.7 the second notable point was the number of people asserting that CAD files are used to describe their systems to their JTAG tooling. While this is not to be discounted, it is by and large the group's experience that the arrangement of boards within a system is rarely documented in CAD in such a way that the system netlist can be extracted. This is perhaps an area that requires further investigation and most probably some work on improving the education given by our White Paper, such that the issues become more apparent.

 


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"Why not" responses:
None.

3.9 - Do you feel SJTAG needs to support modularity of data (re-use of design elements)?

  1. Yes
  2. No

This questions asked about the ability to reuse board level tests at system level. The result here speaks for itself. However, expressing a desire for reuse and making it happen are two different things and that is one of the challenges facing SJTAG.

<2009 Survey, Sections 1, 2 User Survey 2009 Results 2009 Survey, Section 4>