The goal of this study group is to explore the feasibility and to develop a project authorization request (PAR), including the scope and purpose, for an IEEE standard that defines methods to allow, in conjunction with existing methods, for the coordination and control of device, board, and sub-system test interfaces to extend access to the system level, by leveraging existing test interface standards (by defining a description to better manage how they are used in the system).
Among the use cases to be considered by such a standard are structural and functional test, configuration / tuning / instrumentation, software debug, built-in self test, fault injection, programming / updates, root cause analysis, failure mode analysis, power-on self test, environmental stress test, and device versioning.
This new supervisory standard is required to define the coordination and dependencies of instruments as well as configuration, management, and application of vector based testing at the board and system levels, utilizing the pin level access provided by other standards. IEEE 1687 (a.k.a. iJTAG) and IEEE 1149.1-2013 (often referred to as JTAG) provide methods for describing instrument interfaces on a per component basis, but do not provide the contextual prerequisites for the dependence on each instrument configuration and/or aggregation of multiple instruments for the overall board and/or system maintenance operations. Further, many components only support non-JTAG interfaces (e.g., I2C or SPI) to their instrumentation registers.
The study group activity will last for 6 to 12 months, with the intended outcome of the creation of a Working Group to continue the IEEE standardization effort. The group will meet on-line on a weekly basis for one hour long conference calls tentatively scheduled for Mondays at 11am EDT (15:00 UTC), commencing August 14.
Information about past activity of the SJTAG initiative group that resulted in formation of this study group can be found at http://www.sjtag.org.