SJTAG Newsletter


Issue 29 - Q4-2014

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A Tale of Two Domains: Explicit vs. Implicit Selection

(A description of SJTAG Green Papers can be found here.)


In this paper, I plan to present a comparison and contrast to the issues of chain selection as used by several well known use cases for board level testing. During the formation of the IEEE 1687 standard draft, there was much debate regarding whether the test engineer should be responsible for configuring the topology of the scan chain inside of a device or should the tooling be able to automatically configure the topology based on what actions were being applied to the hardware. On one side, engineers like to be able to have control over tools to give them a way to override assumptions a tool uses for cases where they do not match the desired behavior. Further, engineers have to deal with board and chip designs that do not always comply with a given standard. On the flip side, topologies are getting quite complex and it is difficult and time consuming for an engineer to map out and configure the appropriate topology for a given set of actions. This is especially true for actions requiring the selection of different instruments residing down separate hierarchical trees inside of a device. Power management inside devices today complicates this problem even further. If too many methods for selecting a topographical path through a device are used, it becomes a very difficult task for tools to be able to model the sequences that have to be performed in order to select or deselect a particular path. This is even more difficult as you move up in the hierarchy to the board and system levels.

For the discussion in this paper, I will present the hardware and modeling insights of each of the considered standards to give a general overview describing the key aspects of how the mechanism selects the different target registers and how a particular scan chain is able to be removed or ignored from the topology. I will also try to present the key aspects of how these mechanisms are modeled and how they are assumed to be controlled by the tooling. As this is a Green Paper, I will conclude with presenting the issues that I feel need to be addressed by the board and system test community and give insight to the decisions that the SJTAG Study Group has to face.

IEEE 1500 Insights


This standard was the first attempt to standardize the way people accessed a collection of core registers together inside of a chip. The selection of the particular data register to be accessed is controlled by the value residing in the WIR (Wrapper Instruction Register) at the time. The WIR is selected to be wired between the WSI and WSO serial ports of the wrapper using a special selectWIR signal that is controlled by the system integrator designing the Test Access Mechanism (TAM). This may be controlled with the IEEE 1149.1 TAP Controller. There is a WBY (Wrapper BYPASS Register) required by a design to provide a mechanism to bypass a particular core while only adding one additional bit to the scan chain. I am excluding the discussion of the Wrapper Parallel Port (WPP) alternate access from this discussion as we are concerned with the scan chain topology features only for this discussion.

Description: IEEE 1500 Wrapper

Figure 1 Mandatory Components of IEEE 1500 Wrapper


The description of the IEEE 1500 topology and the various commands that may be applied to the wrapper are defined using the Core Test Language (CTL) as defined by the standard IEEE 1450.6. The description for this standard's section 17.1.2.c states, "The intention is for the high-level information model provided by CTL to allow such pattern generation to be possible without need for access to the core's or even the wrapper's netlist definition." This model is to be a high-level model describing only the key aspects required for access and operation.

To read the rest of this article please follow the link below.

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From the Chair

ITC Testweek Update

Description: ITC Logo

Many of you will be reading this shortly after returning from ITC in Seattle - if so, then I hope you had a good trip. I also hope that you managed to stop by our poster during the Wednesday lunchtime Poster Session and perhaps chat with Michele Portolan, our representative on the day.

We were quite fortunate with the location of our poster (near the food table!) and Michele was kept fairly busy during the session. With some of the chip level activities like IEEE 1149.1-2013 and IEEE 1687 now having concluded there seems to be increasing interest in board and system level test once again.

In case you missed the event, you can view our poster on the SJTAG website by following the link below. Unfortunately, you will only be able to download the poster - you've missed the chance to talk to Michele about it!

SJTAG ITC 2014 Poster:

Upcoming Demonstration

On November 17, we will be hosting a demonstration of Michele Portolan's IEEE 1687 (IJTAG) Engine which relies on TISA technologies presented by Michele, Brad and Suresh Goyal in a Design & Test article last year and incorporates some of the Test Manager features that we have been developing within the SJTAG meetings.

This will be conducted via WebEx in our regular weekly meeting slot (Monday at 11 AM US Eastern). If you'd like to join us for this then please get in touch to request a WebEx invitation.

Contact SJTAG:
"Executing IJTAG: Are vectors enough?"


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Next Newsletter

The Q4-2014 edition of this newsletter will be published towards the end of October 2014. Copies of past newsletters are always available on the SJTAG website.

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