The website for the System JTAG Initiative Group and P2654 STAM Working Group

SJTAG - Supporting eXternal and Embedded Boundary Scan Test


At the IEEE European Board Test Workshop held in Tallinn, Estonia, May 2005, a group of 14 board test professionals met to discuss a common set of problems associated with the extended test and configuration use of 1149.1 boundary-scan infrastructure within complex multi-board systems. As a result of this discussion, it was decided to create a system-level JTAG initiative, called System JTAG (SJTAG). It also was decided to create a white paper to more clearly define the nature of these problems and hence their possible solutions.


The goal for SJTAG is: For all variants of XBST and EBST, to define the data contents and formats communicated between external Test Manager platforms and internal Embedded Test Controllers,
between ETCs and the UUTs they serve in an open-standard, vendor-independent and non-proprietary way.

P2654 System Test Access Management:


This standard addresses use/ reuse of test assets in system context by: 1) defining a representation for behavioral descriptions of pertinent sub-assembly interfaces and of relevant data and protocol transformations; 2) defining methods for utilizing such representations to enhance management of and access to said test assets. In conjunction with existing methods for test access and test management, this will allow the coordination and control of a variety of digital interfaces to devices, boards, and sub-systems to extend test access to board and system levels. This standard does not replace or provide an alternative to existing test interface standards, but aims instead to enable their usage throughout the hierarchy of systems.


The purpose of this standard is to facilitate a means to seamlessly integrate component access topologies, interface constraints, and other dependencies at the board and system level by using standardized descriptions focusing on topology, interfaces and behavior (as opposed to physical structure). This will ease the burden on those preparing test, maintenance and support applications, including Automatic Test Pattern Generation (ATPG), in particular where the application requires to co-ordinate control of and data transfer through multiple interfaces and/or protocols. Typically, the providers of these conforming descriptions are the producers of integrated circuits, printed circuit boards or sub-systems, including, for example, intellectual property cores in a System on Chip (SoC), with digital interfaces that are intended to be used in an automated fashion within a larger assembly. This standard will also include a methodology to ensure access to particular destination registers in the correct time order.


Standards exist to access diverse feature sets for device-level test and instrumentation. However, there is currently no standard that provides for the aggregate management and coordination of such standards for higher level assemblies, such as boards or systems.

Users of board- and system-level automated test equipment need to be able to command their tools and instruments, identifying the dependencies, constraints, and required coordination. Embedded applications also need to have access to these same instruments at higher levels during run-time.

Standardization is needed to facilitate such automation and to enhance testability, test coverage, and diagnostics resolution in the higher level assemblies.