Minutes of Weekly Meeting, 2008-11-26

Meeting called to order at 8:20am EST

1. Roll Call

Carl Walker
Eric Cormack
Brad Van Treuren
Patrick Au
Heiko Ehrenberg

Ian McIntosh
Peter Horwood

2. Review and Approve Previous Minutes

11/17 Minutes: motion by Brad, second by Patrick

3. Review old action items

  • Adam proposed we cover the following at the next meeting:
    • Establish consensus on goals and constraints
    • What are we trying to achieve?
    • What restrictions are we faced with?
  • Establish whether TRST needs to be addressed as requirements in the ATCA specification if it is not going to be managed globally (All)
  • Adam review ATCA standard document for FRU's states
  • Ian to contact Rohit regarding IEEE policy for interviews.
    Ian queried policy for sanctioning interviews, vetting content, stating disclaimers, etc., once were are formally constituted under the IEEE/TTSC. The response was that we were free to conduct whatever interviews we wish: TTSC will not interfere.
  • Patrick contact Cadence for EDA support person.
    Expect report if Patrick attends 26/11 meeting.
    * tried contacting them, no response yet; not sure if his contact is still there (had layoffs)
  • All - Consider what data items are missing from Data Elements diagrams for Test Program Generation [See discussion topic 4c of 11/17/08].
  • Eric - Make initial contact with Synopsys on possible EDA participation [Done - See discussion topic 4b of 11/17/08]].
    * Robert Ruiz, Product Line Marketing Manager, confirmed their monitoring of our activity, but SJTAG is not a priority for them

4. Discussion Topics

    1. White Paper Section Status
      • i) Volume 1 - Overview Document: no additions/changes done;
      • [Brad] we had consensus in a prior meeting that this is pretty much set for now;
      • ii) Volume 2 - Use Case Document:
      • [Heiko] still needs quite some work
      • iii) Volume 3 - Hardware Architectures Document:
      • [Carl W.] no changes/additions; have notes that need to be worked in
      • iv) Volume 4 - Languages and Data Formats Document:
      • [Brad] this is still in its infancy; noone has been assigned yet
      • v) Volume 5 - Business Document:
      • [Brad] no
      • proxy submission by Ian:
        I'm not really expecting anything to have moved on here, but as it's a few weeks since we looked at this I just wanted to raise a gentle reminder that these still need work. Probably "the Carls" with Volume 3 have the greatest potential for making progress right now. I'd also like to get some idea of how people might expect Volume 5 (Business Case) to shape up.
        Brad might have some ideas?
        I haven't made any changes to anything on White Paper sections recently. I guess it'll be the same for most other folks. I don't think there's much more I can do with Vol 1 - maybe Brad can check over to see if there's anything missing.
        For Vol 4, I think languages might be something that will take time to develop; data on the other hand seems like something we ought to be able to get to grips with fairly quickly.
        I'm not at all sure how Brad envisaged the Business Case being presented in Vol 5 - It seems like the Value Propositions from the Use Cases will be a major part of this, so there's no point in duplicating that content.


    1. EDA participation
      • proxy submission by Ian:
        I'm hoping Patrick will have something to report. I gave Eric some material to relay to his Synopsys contact, so he may also have a further update, but it may be too soon for anything positive.
        I haven't spoken to Mentor in the past week (I'm on "short weeks" just now to use up my vacation allowance before the year end), However I'm going to try to contact Lyle Pittroff (the author of the article that Brad forwarded a couple of weeks ago) during the course of this week.
      • [Patrick] tried contacting them, no response yet; not sure if his contact is still there (had layoffs)
      • [Eric] Robert Ruiz, Product Line Marketing Manager, confirmed their monitoring of our activity, but SJTAG is not a priority for them


    1. Follow-up survey
      • proxy submission by Ian:
        We had intended to run the follow-up survey "later this year", but with recent events, I think we've timed out. Even if we had all the questions to hand right now, I'd struggle to get the web forms assembled and published before the year end. Is there anything that might drive a timeline for this?
        I expect the main driver will be when we can define the content - the previous discussions can be found in the minutes starting with 6/4 (http://www.sjtag.org/minutes/minutes080604.html). Should we use the opportunity to get views on data elements and sources? Ask about languages in use? Do we feel we can ask what tools people use? I don't expect any conclusions at this meeting - just re-start the thought processes.
      • [Eric] do we ask what tools people use? I think we should; we need to know which tool vendors to approach; from those answers we can also draw some conclusions regarding language requirements / support;
      • [Patrick] is it true to say Cadence is the major in board level EDA?
      • [Eric] I think Mentor and Cadence keep fighting for the lead, with Cadence maybe leading at this point;
      • [Patrick] regarding tool vendors I think we need a set standard before approaching them
      • [Eric] for the "small" vendors [such as the Boundary Scan tool vendors] I would expect them to get interest with a more defined standard draft and when a customer comes to them asking for SJTAG support
      • [Brad] a significant issue with Cadence and Mentor is the relationship between chip design community and board design community is very divergent, both types of tools don't provide much synergy; such a synergy is something we need for well defined data elements, though;
      • [Eric] yes, there is definitely a problem with the tool flows
      • [Brad] coming up with a common process for using the tools is very difficult too; everyone is using the tools differently and data resulting from the various processes does not lend itself for easy comparison / common post processing
      • [Eric] the survey results could show us the type of influences people are looking for
      • [Heiko] do we have a timeline we want to see this follow-up survey realized in?
      • [Eric] end of January / early February ?
      • [Brad] I'd agree


  1. Data Element validation vs Structural Test Use Case (continuation)
    + Data to support execution and diagnostics
    • proxy submission by Ian:
      I don't want to bore people by continuing on the ATPG aspects at another meeting, so I've started a thread on the Forums in SJTAG Forum Index > SJTAG General Discussions > Descriptive data for non-BScan devices (http://forums.sjtag.org/viewtopic.php?t=82) where we can follow up.
      Instead, I think it's probably important to start to look at data required to support diagnostics as I think this could be a complex area when you consider the different (and possibly conflicting) requirements of external and embedded Test Managers. We need to concentrate on WHAT the data is and WHERE it comes from and not get too hung up on how it is formatted - I think that's a mistake we made last meeting.
      Brad has thought about this some, so I'm sure he will get the ball rolling.
    • [Brad] there are different application flows with regard to SJTAG:
        - pure embedded w/ real-time diagnostics (see also BTW2006 paper http://files.sjtag.org/BTW2006/BTW2006-Van-Treuren.pdf)
        - execution is embedded, diagnostics is external (various approaches have been demoed in the last two years)
      In order to do diagnostics, we need a mapping from global BScan cell location back to device and pin location (this BScan cell is assigned to) and to the net this pin is connected to; each test type may require different forms of information; can we represent the circuit model in a way that provides the information needed by all the different types of tests?
    • [Brad] for system perspective, we also need information about board location
    • [Eric] yes, and also the module level
    • [Brad] instance specific information will limit the re-usability, though;
    • [Eric] hierarchical representation is important
    • [Heiko] we should come up with a list of tests that we are looking at here
    • [Brad] - 1149.1 BScan to BScan connectivity test,
                  - 1149.6 BScan to BScan connectivity test,
                  - BScan to non-Bscan to BScan cluster test,
                  - memory connectivity test,
                  - FLASH connectivity test
    • [Heiko] structural tests using functional access mechanism rather than BScan cells (emulation for example) may not be representable in such a standardized diagnostics database
    • [Brad] BIST, etc.
    • [Eric] should we also look at "reduced pin count test", which is widely used at the chip level?
    • [Brad] sources for the data we need:   - net from netlist   - device pin and cell from BSDL file (naming of pin between BSDL and netlist must be the same)   - mapping to global chain - this is the missing piece right now (everyone is defining it their own way)
    • [Patrick] what about unused pins (pins not listed in the netlist)?
    • [Brad] depending on the type of pin [BScan cell] such unused pins can still be included in tests
    • [Brad] do we feel SJTAG is requiring a new test language to obtain the information needed for diagnostics or is STAPL/SVF sufficient?

5. Schedule next meeting

Monday, December 8th, 2008, 8:15am EST
Monday, December 15th, 2008, 8:15am EST

6. Any other business

  • meeting time for future meetings
    • proxy submission by Ian:
      I'd like to ask whether the present timing of the meetings is still the most suitable. As I see it, 8:15 Eastern is probably "early" even for the East coast and makes it really hard for anybody further West. I'd guess that part of the reason was to let Brad hold the meeting before the main chaos of his day broke out. Anthony Sparks is keen to join, but 5am is just too big an ask! If the EDA people take an interest, then their locations may need to be considered too.
      On the other hand moving later may make it harder for central and Eastern Europe - we have no representation there right now, but that could change.
      Maybe we can poll the group again for the 2009 schedule (as we did for this year)?
    • [Brad] 8:15am was driven by the folks at Huawei in China
    • [Patrick] how about 4pm GMT, then I could join Monday and we don't need a Wednesday meeting
  • Ian said his NTF presentation went well

7. Review new action items

  • [All] do we feel SJTAG is requiring a new test language to obtain the information needed for diagnostics or is STAPL/SVF sufficient? see also Gunnar's presentation, in particular the new information he'd be looking for in a test language (http://files.sjtag.org/Ericsson-Nov2006/STAPL-Ideas.pdf)
  • [All] does the new proposed meeting time for Mondays: 4pm GMT (http://wwp.greenwichmeantime.com/) work for you? do we still want to hold Wednesday meetings?

8. Adjourn

Meeting adjourned at am 9:31am EST (Moved by Eric, Second by Patrick)

Respectfully submitted,