Minutes of Weekly Meeting, 2010-02-15

Meeting called to order at 10:36 AM EST

1. Roll Call

Adam Ley
Brad Van Treuren
Peter Horwood
Eric Cormack
Ian McIntosh
Tim Pender
Heiko Ehrenberg
Michele Portolan (joined 10:52)

Patrick Au
Carl Walker

2. Review and approve previous minutes:

02/08/2010 minutes:

  • Draft circulated on 8th February:
  • Two corrections noted:
    • Delete "Proposed agenda"
    • [Carl] Evan at the daughter board level this is important -> Even
  • Tim moved to approve with the above corrections, seconded by Brad; no objections or abstentions.

3. Review old action items

  • Adam proposed we cover the following at the next meeting:
    • Establish consensus on goals and constraints
    • What are we trying to achieve?
    • What restrictions are we faced with?
  • Establish whether TRST needs to be addressed as requirements in the ATCA specification if it is not going to be managed globally (All)
  • Adam review ATCA standard document for FRU's states
  • All to consider what data items are missing from Data Elements diagram
  • All: do we feel SJTAG is requiring a new test language to obtain the information needed for diagnostics or is STAPL/SVF sufficient? see also Gunnar's presentation, in particular the new information he'd be looking for in a test language
  • Ian/Brad: Draft "straw man" Volume 4 for review - Ongoing
  • All: Review "Role of Languages" in White Paper Volume 4 - Ongoing
  • All: Review 'straw man' virtual systems and notes on forums:
    http://forums.sjtag.org/viewtopic.php?f=29&t=109. - Ongoing
  • All: Add to, or comment on, the bullet point list of architecture drivers. - Ongoing.
  • All: Provide forum comment on the graphics used during the meeting; suggest "building blocks" that may be used in future:
    http://forums.sjtag.org/viewtopic.php?f=29&p=257#p257 - Ongoing.
  • All: to think about topics for upcoming Winter newsletter and submit to Ian via email - COMPLETE - See topic 4b.

4. Discussion Topics

  1. How to progress revision of Volume 3
    • [Ian] I wanted to revisit last week's topic first. I had hoped to read over the minutes more fully first but I haven't really had the time.
    • [Ian] One thing I wanted to comment on that seemed relevant, and has been coming up a lot here over the last couple of weeks, is the support for using device vendor tools. Quite a few of the hardware guys here want to be able to use their emulation pods or Xilinx pods with Chipscope. To do that they want the gateway's to be transparent, with no synchronization bits being added.
    • [Brad] I've been involved in similar discussions here.
    • [Ian] That can limit the choice of gateway device. The TI ASP could go into a transparent pass-through. The orignal LASP datasheet suggested it did the same, but one of our guys tried it and it still had padding bits. I believe the datasheet has now been amended.
    • [Brad] Yes, we ran into similar problems here.
    • [Peter] As you know our parts have that, so you can connect your emulation pods as if they were directly on the device.
    • [Brad] It's an important issue. It's why product groups are designing their own solutions for the chain selection. But it creates problems for the tooling to understand the chain selection.
    • [Ian] Yes, one of our partner companies designed a board for us like that and it a took a bit of effort to instruct the tooling about the chain selections.
    • [Brad] In one case, the configuration was by I2C, and trying to integrate that was a nightmare. We had to interject system commands in amongst the boundary scan, so it was no longer a single board involved in the test.
    • [Brad] The tooling we have, most BScan tooling in fact, supports the LASP, so it's not a show stopper, as it might have been a while back.
    • [Tim] But that means that they need to come to you if they want to reprogram something?
    • [Brad] Yes, essentially.
    • [Ian] Yes the BScan specialist tooling is generally OK with these parts now, it's just the device vendor tools that not so tolerant of third party parts.
    • [Brad] And sometimes the third party part need to be the first device in the chain.
    • {Michele joined}
  2. Draft of Winter Newsletter
    • [Ian] I sent out a draft Newsletter last night. It was put together in a bit of a hurry.
    • [Eric] There are some spelling errors: In the second paragraph you have "they" where it should be "the" and "appy" instead of "apply". Then there's "ha" for "has"; in the third paragraph there's "tht".
    • [Eric] In the bit on the survey "get" is missing - "get into offices". There's a "have" missing in the last paragraph there.
    • [Ian] I told you I did it in a hurry. I didn't even take the time to run it through the spell checker.
    • [Tim] In the News section there is "he" twice when it should be "The". A spell check would pass that.
    • [Tim] The first paragraph of From the Chair uses "while" twice; that seems like too many and maybe one should be "as" instead?
    • [Ian] I'll correct those things. Is there anything we think we should add?
    • [Brad] I think maybe we should mention that we're working on Volume 3 of the White Paper, and that we're using some of the feedback from the survey to guide us, without being specific about what information we're using.
    • [Ian] That sounds like a good idea. I'll write something up for next the meeting and correct the errors at the same time. {ACTION}
  3. Review of Survey Results
    • Q3.7/3.8
    • [Ian] We were going to look back at the tables for Q3.7 and Q3.8.
    • {Result table shared}
    • [Ian] Brad was probably the one try to determine something from this, but I know he's been busy.
    • [Brad] I haven't really had the bandwidth to look at this yet.
    • [Ian] I originally expected to see a pattern between how people answered 3.7 and 3.8, but there isn't really an obvious one. VHDL is widely used at the board level but much less so at the system level.
    • [Tim] Probably because VHDL is used to describe some design element like an FPGA, and that is less applicable at the system level.
    • [Ian] I'm sure that's right.
    • [Brad] I think it suggests that not all HSDL users are using VHDL.
    • [Ian] I don't understand people who say they're using the CAD files at the system level but not at the board level. It seems counterintuitive to me, and I think that's your experience too Brad?
    • [Brad] Yes it is. Someone last week mentioned the subject of signal naming and the interface between boards and the backplane.
    • [Eric] I was talking about some in-house tooling, scripts that could resolve much of the signal names changing as you went across boundaries.
    • [Ian] I had a discussion with one of our guys who is preparing the internal ICD for one of our units, and I described the problems that these almost arbitrary choices of signal name can create. He quickly understood the problem and said that he'd ensure that the names used at each interface would easy to reconcile. It isn't hard once people understand the reasons.
    • [Brad] That's OK for your own product, but we can have some parts that come from different product areas, or things that are reused in other products.
    • [Ian] That is true; I guess we're relatively lucky in that we're generally pretty self-contained that way. But not always.
    • {Main survey charts shared}
    • Q6.8
    • [Ian] Here we seem to have a group leaning towards smaller memory sizes and another going for bigger sizes and a gap in between.
    • [Brad] I wondered if this was the difference between mobile application and the larger server type applications.
    • [Ian] Possibly, but it might be hard to determine now. We might get some indication by correlating with each person's market sector?
    • [Brad] Those smaller memory really preclude any big FPGA updates.
    • [Ian] Yes, but again this is like Q6.7, in that the question specifically mentions "testing". Maybe we should have worded the question differently.
    • [Brad] Yes, something to learn. Those sizes are realistic for testing.
    • Q6.9
    • [Brad] I'm surprised at "Central Repository" scoring so highly here. When you account for the build variations, a cental repository can become a maintenance nightmare.
    • [Ian] I expected "JTAG Plug 'n' Play" to score best.
    • [Brad] Maybe a lot of people don't quite understand what that is though.
    • [Brad] It'd be interesting to see if the responses fall into two camps; the "a and b" and the "b and c" camps.
    • [Ian] Actually from the results it seems to be mostly "a, b and c" with a few "b" only on top.
    • [Brad] That's what I was afraid of; that doesn't really tell us anything. So maybe the value is in the comments?
    • [Ian] Well one of the comments is about the storage of results rather than the storage of the tests.
    • [Brad] So maybe where you store the results is more important than where you store the tests.
    • [Ian] Yes, and that's not a question we asked.
    • Q7.1
    • [Brad] Only one person thinks that standardized gateway access is unnecessary.
    • [Ian] This rather ties in to our earlier discussion. If the access methods were described in a standard then vendor tools are more likely to support gateways. But it's a bit of a chicken and egg problem.
    • Q7.2
    • [Ian] A fairly even spread of responses, although I guess that a and c are not mutually exclusive; perhaps even b.
    • [Brad] Option b is more restrictive.
    • [Ian] The second comment says you need to describe how the selection actions are performed, not just tell the tool which selection has been made.
    • [Brad] It's be interesting to see if that person is an HSDL user.
    • [Ian] Yes they are, so it suggests that they're not satisfied with HSDL as it stands.

5. Schedule next meeting

Schedule for February 2010:
Monday February 22, 2010, 10:30 AM EST

Heiko will likely miss 22 Feb.

Schedule for March 2010:
Monday March 1, 2010, 10:30 AM EST
Monday March 8, 2010, 10:30 AM EST
Monday March 15, 2010, 10:30 AM EDT
Monday March 22, 2010, 10:30 AM EDT
Monday March 29, 2010, 10:30 AM EDT

6. Any other business


7. Review new action items

  • Ian: Add Newsletter section on Volume 3 work and correct existing errors.

8. Adjourn

Peter moved to adjourn at 11:37 AM EST, seconded by Eric.

Respectfully submitted,
Ian McIntosh