Minutes of Weekly Meeting, 2011-12-19

SJTAG conference call on December 19, 2011
Call to Order:
11:05 am EST

1. Roll Call:

Eric Cormack
Carl Walker
Heiko Ehrenberg
Brian Erickson (call-in user 1)
Tim Pender (joined at 11:10am)

Excused Absences:
Patrick Au
Brad van Treuren
Ian McIntosh
Adam Ley

2. Review and approve previous minutes:

Approval of December 5 minutes (draft sent 6 December):

  • Corrections: None noted
  • approval deferred, no quorum

Approval of December 12 minutes (draft sent 12 December):

  • Corrections: None noted
  • approval deferred, no quorum

3. Review old action items

  • Adam proposed we cover the following at the next meeting:
    • Establish consensus on goals and constraints
    • What are we trying to achieve?
    • What restrictions are we faced with?
  • All: do we feel SJTAG is requiring a new test language to obtain the information needed for diagnostics or is STAPL/SVF sufficient? see also Gunnar's presentation, in particular the new information he'd be looking for in a test language
  • Ian/Brad: Condense gateway comments and queries into a concise set of questions. - Ongoing
  • All: Forward text file to Ian containing keywords from review of meeting minutes. - Ongoing.
  • Carl/Brad: Get annotated keyword worksheets to Ian by Wednesday Close of Business. - Ongoing
  • All: Consider how a keyword can be used to define the chain configuration for a given test step, and what that keyword might be.
  • Harrison: Prepare slide showing matrix of industry sectors by volume/mix. - Ongoing.

4. Discussion Topics

  1. Languages and descriptions
    - Refer to 2009 survey Q3.5-Q3.8
    • In Q3.5 which do we think is related to structure and which to control/behaviour?
    • Eric: System Verilog?
    • Heiko: VHDL, NSDL, HSDL (part of 1149.7, but maybe just for scan chain?)
    • Tim: I believe HSDL also for merging net lists
    • Eric: merging net lists would become important for us, wouldn't it?
    • Eric: STAPL got quite a few nods, would that be suitable for SJTAG;
    • Heiko: yes, in the early days of SJTAG STAPL (and extensions to it) has been discussed quite a bit (see also our document archive on the SJTAG website)
    • How might these relate to ICL, PDL?
    • Tim: I think any higher language language we are choosing would need to be able to be integrated with the target system would be working with
      (e.g. for turning on/off power, controlling system functions, etc.);
    • Do the subjects in Q3.7 and Q3.8 describe more than structure?
    • Heiko: at least a few of those language should be able to describe behavior/control as well (VHDL, Verilog, for example)
    • Tim: many tools can export to VHDL; tools then should be able to merge VHDL files for board level (e.g. Menor DxDesigner)
    • Tim: board level VHDL would describe the in's and out's of the board; system VHDL could then merge those board interfaces;
    • Tim: problem might be various possible configurations; would need some tool that can handle the dynamic possibilities of system hardware configurations;
    • Heiko: interesting idea; that would also allow people to hide details about the system
  2. Harrison's industry sector matrix (if available)
    • not present

5. Key Takeaway for today's meeting

- languages listed in Q3.5a through Q3.5i don't define structure of a system

6. Schedule next meeting

Schedule for January 2012:
9th, 16th, 23rd, 30th; same time (11am EST)

7. Any other business


8. Review new action items


9. Adjourn

due to slow moving discussion we decided to shorten the meeting;
Eric moved to adjourn at 11:40am, Tim seconded

Adjourned at 11:41am