Minutes of Weekly Meeting, 2012-06-18

Meeting called to order: 11:05 AM EDT

1. Roll Call

Ian McIntosh
Carl Walker
Heiko Ehrenberg
Brian Erickson (left 12:08)
Peter Horwood
Patrick Au
Brad Van Treuren
Adam Ley (joined 11:07, left 12:04)

Eric Cormack

2. Review and approve previous minutes:

06/11/2012 minutes:

  • Draft circulated on 06/11/2012.
  • No corrections noted.
  • Brian moved to approve, seconded by Carl. No objections or abstentions.

{Adam joined}

3. Review old action items

  • Adam proposed we cover the following at the next meeting:
    • Establish consensus on goals and constraints
    • What are we trying to achieve?
    • What restrictions are we faced with?
  • All: do we feel SJTAG is requiring a new test language to obtain the information needed for diagnostics or is STAPL/SVF sufficient? see also Gunnar's presentation, in particular the new information he'd be looking for in a test language
  • Heiko to prepare overview of proposed updates for 1149.1 - Ongoing. Heiko expects to have this ready for next meeting (June 25). - Ongoing.

4. Discussion Topics

  1. What is the current 'state of the art' for SJTAG applications?
    - What do current applications achieve and how do they do it?
    - Discussion around Brad's presentation on Embedded JTAG from 2002.
    • {BTW2002_2.3_Slides.pdf shared} Brad discussed a selection of the slides.
    • {Slide 2} Embedded tests need all resources to be present in the system, so leverage existing resources already present for functional test.
    • {Slide 6} Embedded test software supports data compression and test identification. TFCL provides high level control of the 'test steps', with dynamic flow control depending upon test step outcome. TFCL knows about test steps but not that they are SVF or STAPL, etc.; test flow control decoupled from test data. Implemented as API (in C++) and exploits OO techniques to reduce size. Adding a new test step doesn't require new firmware code.
    • {Slide 7} Test Flow Control Language example. APPLY causes a test step to run, FROM and TO indicate data passed to a test step, while DIAGNOSE is a keyword passed to the test step, e.g. what kind of result is expected. There is implicit state information (Pass/Fail) that can be used in conditional statements.
    • {Slide 8} Embedded test station overview diagram. Includes the development environment. STEM is Lucent's Serial Test Extension Module - provides board boundary I/O to emulate the backplane installation. Similar to the Firecron/ Asset demonstration in terms of architecture. Original implementation was loaded into the target using the debug monitor as no O/S or system software was ready.
    • {Slide 9} Embedded test generation process. Upper left area is conventional test development iteration, but takes the lab tests and adds in the constraints that form the backplane considerations. From this a SVF is exported which is then converted into form suitable for loading onto the target (S-Record in this case). The test is then verified in situ.
    • {Slides 10, 11, 12} Highlighting specific steps in the development process. For 12, noted that this step is essential to confirm that the test is not triggering some event that it shouldn't.
    • {Slide 13} Duplex case study - a fault tolerant controller, with dual port memory accessible by both controllers. Active controller tests the stand-by controller (which is which can change). 51% test coverage with constraints in place. Test vectors stored in Flash and pulled via the dual port memory.
    • {Slide 14} Simplex case study - Controller board tests Feature boards, including the feature element on itself. Considering this introduced the problem that might arise if a given feature board was given new artwork that changed the associated test, and the problems in maintaining the test repository. Test vectors could be drawn from an external database.
    • {Slides 15, 16} Summary of benefits. Improved diagnostics compared to functional test with no external setup or hardware. Tests and diagnostics usable throughout product life cycle and in various test environments. Gives failure diagnostic (fail at site) not fault diagnostic (e.g. stuck at). Plug and Play discussed elsewhere to address the test data management issue. SVFs typically compress by 70%, but needs sufficient RAM for decompressing and will extend test time.
    • {Slide 17} Traps and pitfalls of embedded test. Extremely important: Fault recovery strategy needed (how to recover from a defect, how to recover from boundary scan test mode back into an operational mode), and the method is probably not what you'd do after a functional test. Mostly, you need to reboot that board. Ideally you want architecturally isolated control hardware but that's not always possible. Issues exist with test data management/versioning, and with chain configuration management, even after 10 years.
    • {Slide 18, 19} Conclusions. An extension toi external testing but with additional constraints. Embedded test = built-in test, allowing you to run tests anywhere. Hooks need to be in place: Better to get the hardware hooks in first and allow the software to come along later.
    • {Adam left}
    • Can't always get true reuse, but salvage helps amortize development costs. May be opportunities to economize on functional test without loss of coverage. Location of test data will influence data management cost.
    • {End of slides}
    • Brad highlighted that what was discussed here was essentially the same as the architecture Peter had described in the previous meetings, but with the Test Manager moved to an embedded position. The building blocks were present and the same data elements were being moved around. Ian will add a reference to the BTW paper in the notes and make the slides available on the SJTAG website. {ACTION}
    • The accompanying paper to the slides used today is located at: http://btw.tttc-events.org/material/BTW02/btw02-2-3.pdf

5. Key Takeaway for today's meeting

Today's slides use the same SJTAG architecture as the Asset/Firecron demo; the same data elements are moved between the Test Manager and Test Controller, only the Test Manager has been relocated to be inside the system. Embedded test generation process: circuitry on interfaces/backplane needs to be constrained; finding the proper constraints is an iterative process.

6. Schedule next meeting

June 25 - Brad is likely to be absent.

July schedule:
2, 9, 16, 23, 30
Carl, Patrick and Ian are likely to be absent on July 2. Decide next week if the meeting should be cancelled for that week.

7. Any other business


8. Review new action items

9. Adjourn

Patrick moved to adjourn at 12:13 PM EDT, seconded by Peter.

Thanks to Heiko for providing additional notes this week.

Respectfully submitted,
Ian McIntosh