Minutes of Weekly Meeting, 2012-06-25

Meeting called to order: 11:05 AM EDT

1. Roll Call

Ian McIntosh
Carl Walker
Patrick Au
Heiko Ehrenberg
Brian Erickson
Eric Cormack
Adam Ley (joined 11:07, left 12:04)
Brad Van Treuren (joined 11:16)
Tim Pender (joined 11:35)
Harrison Miles (joined 11:40)

Peter Horwood

2. Review and approve previous minutes:

06/18/2012 minutes:

  • Draft circulated on 06/18/2012.
  • No corrections noted.
  • Patrick moved to approve, seconded by Adam. No objections or abstentions.

3. Review old action items

  • Adam proposed we cover the following at the next meeting:
    • Establish consensus on goals and constraints
    • What are we trying to achieve?
    • What restrictions are we faced with?
  • All: do we feel SJTAG is requiring a new test language to obtain the information needed for diagnostics or is STAPL/SVF sufficient? see also Gunnar's presentation, in particular the new information he'd be looking for in a test language
  • Heiko to prepare overview of proposed updates for 1149.1. Heiko expects to have this ready for next meeting (June 25). COMPLETE.
  • Ian: Make the slides used today available on the SJTAG website. COMPLETE.

4. Discussion Topics

  1. Overview of changes proposed for 1149.1-2012.
    • {new in IEEE 1149-2012.pdf shared}
    • Heiko presented his summary of the changes currently being proposed for IEEE Std. 1149.1, noting that he did not intend going into too much detail.
    • {Slide 1} Although previously touted as 1149.1-2012 it was looking more likely to be 2013 before this revision is complete.
    • {Slide 3} The previously deprecated BC_6 cell is now no longer supported. A boundary scan register can consist of several segments, any of which may be optionally excluded. All pins, other than TAP signals, may have observe-only cells. Flow-up of 1149.1.1 interface definition for the TDR.
    • [Heiko] Redundant observe-only cells are now allowed on
      • the individual pins of a differential pair,
      • compliance enable, analog, power, or other pins where no cell is required
      (when observing non-digital pins, they will normally capture a fault condition; there is no restriction on the number of fault detection circuits or cells that may be associated with a single component pin.)
    • {Slide 5} New Test-mode Persistence Controller, provides support for test as part of a BIST, etc. Instruction to read ECID; only method of access is defined, not the format or content. The concept of Initialisation existed in 1149.6 but is now moved to 1149.1. New method to control IC level resets, beyond simply controlling TLR. Option to control power domains; exclude a domain if it is powered down. A register can consist of several 'segments' which are assembled into a complete register. Extensions to BSDL and a form of PDL introduced.
    • {Slide 6} TMP Controller has two states; on or off. Defaults to off on power up. When on, Test-Mode is maintained even for instructions that would normally drop out of Test-Mode. Associated 2-bit control register: Persistence on/off and set/reset BYPASS-Escape, the latter being a setting to allow a BYPASS instruction to turn off the persistent state.
    • [Heiko] Place and hold the device in test mode (pins are controlled from boundary-scan register);
      Specifically provided for ICs with design specific TDRs controlling internal tests and ICs that support initialization, but should be useful in many other situations;
      TMP controller enables safe use of on-chip test capabilities when the IC is in-system and also reduces unnecessary reloading of the initialization data and boundary-scan register between 1149.1 based PCB tests; The TMP controller shall change state only in response to the following events:
      • A rising edge of TCK when either the CLAMP_HOLD or CLAMP_RELEASE instructions are active (see Clause 8.20); or
      • A transition to logic 0 at the TRST* input (if provided, see Figure 6-8); or On-chip reset at power-up (i.e. POR, if provided, see Figure 6-8); or
      • A rising edge of TCK when the single-bit TMP control register is asserted (it contains a ‘1’), and the BYPASS instruction is in the Instruction Register and the TAP controller is in the Update-IR TAP controller state.
      Loading of IDCODE instruction or BYPASS instruction by entering the Test-Logic-Reset TAP controller state does not reset the TMP controller state (since the TAP state does not pass through Update-IR).;
      TMP control register is selected for scanning by the CLAMP_HOLD instruction; TMP controller state shall not be altered by the operation of any system input, including a system reset input;
    • {Slide 7} Standardized means for fetching the ECID, device remains in functional mode.
    • [Heiko]ECID value is unique to the individual chip, within all chips of the same type;
      Operation of the ECID register has no effect on the operation of the on-chip system logic;
    • {Slide 8} Initialization mainly focussed on devices with programmable IO, and provides three new instructions. The process needs to be in PDL if it is more than just applying the INIT_RUN instruction. Initialized state is retained through TLR if TMP is 'on'.
    • [Heiko] Purpose: get the device ready for test (safe and cool) Configure I/Os and put internal function blocks into states to keep the component 'safe and cool' in board test environment;
      Data provided by the initialization procedures and loaded by the INIT_SETUP or INIT_SETUP_CLAMP instruction may vary from instance to instance, and board to board;
      If provided, INIT_SETUP must be run before INIT_SETUP_CLAMP;
      INIT_RUN instruction, if provided, must be run prior to any other test-mode instruction other than the INIT_SETUP_CLAMP instruction;
      The INIT_SETUP and INIT_SETUP_CLAMP instruction pair, and the INIT_RUN instruction are each optional and independent. One can exist without the other. If INIT_RUN is provided and requires parameters, then all three instructions must be provided.
    • {Slide 9} Reset of the device ('system' reset) uses Reset-Selection register to command multiple internal resets.
    • {Slide 10} Registers may be segmented. Segments are fixed length, at least 1-bit long and cannot overlap. Recent proposals may allow nesting of segments. Segments excluded by default and included only if corresponding segment-select cell is set.
    • [Heiko] If the boundary scan register is segmented, then signals driven from component pins controlled by an excluded segment will be determined by system logic (functional mode) while test mode instructions are active (CLAMP, EXTEST, ...); HighZ will always tristate functional outputs;
      Excluded TDR segments do not respond to Update-DR;
      Segments can be reused in multiple registers, but each combination of segments must have a unique register name;
      Note that 1149.1 now also includes a recommendation for a specific TDR interface for design specific TDRs (table 9-1)
      Register segments do not require any additional instructions other than the one selecting the register for scanning;
      Segment-select cell controls inclusion combined with a switching circuit, such as a MUX (logic 0 = exclude; logic 1 = include);
      Prior to inclusion, status can be captured to determine if the segment is ready to be scanned (capture logic 1) or not (logic 0);
      In initialized state, the register must have a non-zero length, which is specified in BSDL;
      * = This restriction is true for registers defined in the standard; design-specific registers may have nested excludable segments; and in that case any excludable segment that appears within another excludable segment shall be completely enclosed within that segment;
    • (Slide 11} Power domain control allows unpowered sections of a device to be excluded while maintaining the boundary scan path.
    • [Heiko] Power domain-control cell and segment-select cell may be in the same test data register (TDR) as the excludable segment, or they may be in a different TDR that acts to configure the chip for test (e.g. the init-data register);
      These control cells (as well as the controlled cells/segments) must be in public (standard or design-specific) TDRs;
      Boundary-scan register segment domain-control (DomCtrl) and segment-select (SegSel) cells are restricted to be provided in boundary-register and/or init-data register;
      Domain control cell must be in a non-excludable portion/segment of a TDR.
    • {Slide 12} BSDL additions to help describe segmented registers.
    • [Heiko] BSDL mechanisms for documenting and naming the fields of Test Data Registers, and of providing named constants for those fields.
    • {Slide 14} New instructions are all optional.
    • [Heiko] Test-mode instruction: any instruction that interferes with the flow of signals between the system pins and the on-chip system logic.
    • {Slide 15} CLAMP_HOLD is required if TMP Controller is present, activates Persistence-On. May use any non-zero opcode of the chip designer's choice.
    • {Slide 16} CLAMP_RELEASE is required if TMP Controller is present, and will also set Persistence-Off. May use any non-zero opcode of the chip designer's choice.
    • {Slide 17} TMP_STATUS reports the states of the TMP controller and the BYPASS-Escape bit. Chip designer chooses opcode.
    • {Slide 18} ECIDCODE returns the device ECID or all 1s if there is a problem in recovering the data.
    • [Heiko] Electronic chip identification (ECID) is a 'serial number' for the component which may be permanently encoded into the component during the manufacturing process in order to permit tracking the history of the components through their lifetime;
    • {Slide 19} INIT_SETUP loads the Init Data register. Data is likely to be dependant on where the device is mounted. Device remains in functional mode. If provided, it must be used before any test mode instruction. Brad asked if there were any safeguards to ensure that happened - Heiko believes that it is simply a rule.
    • [Heiko] Effects of the information supplied by the INIT_SETUP instruction, such as powering-up domains, including boundary-scan register domains containing I/O, turning PLLs on or off, can take effect immediately; So while the instruction is not a test mode instruction, it can be disruptive to both the I/O and the system logic.
      INIT_SETUP instruction, if provided, must be run prior to any instruction that interferes with the flow of signals between the system pins and the on-chip system logic.
    • {Slide 20} Adam gave some background to INIT_SETUP_CLAMP: The original intent was that INIT_SETUP would be nonintrusive, but it was later argued that in some cases it would be difficult to avoid all interference, so it was partially intrusive. This is a test mode twin to INIT_SETUP. Brad asked if this was really an either/or case, but Adam explained that the higher level tests may require the clamped version or not and that this was rather like the difference between BYPASS and CLAMP.
    • {Slide 21} INIT_RUN starts a sequential initialization process (in PDL). Completion may wait for a specified time or number of clocks or may poll.
    • [Heiko] Initiates and provides the time for an internally controlled sequential (state machine) initialization process, optionally using information provided by the INIT_SETUP instruction;
      If sequential initialization process is not required, INIT_RUN does not need to be provided;
    • {Slide 22} IC_RESET does not effect TAP logic or TMP controller state. May replicate one or more physical reset pins although resets need not have any corresponding physical pins.
    • [Heiko] purpose of this instruction is to provide test control of the system reset and related inputs, regardless of the response of the system logic to the system inputs;
    • {Slide 24} New data register are all optional.
    • {Slide 25} TMP Control Register is a 2-bit register: Bit 0 is BYPASS-Escape bit and Bit 1 is the TMP-status bit. Diagram in Slide 26.
    • [Heiko] Allows polling of TMP Controller Status (Persistence on or off?), register bit closest to TDI (captures 1 in case of 'Persistence-On').
      Allows setting of Bypass-Escape bit (closest to TDO), which when loaded with 1 would force Persistence off when BYPASS instruction is made active.
    • {Slide 27} Electronic Chip ID (ECID) Register has length and content defined by the manufacturer. Harrison expressed an opinion that there may be a move to standardize on the format and content as move towards dealing with counterfeiting. Ian thought that was likely to happen in future but that the idea right was probably not to impose any additional burden on the vendors to change any identification systems they already use.
    • [Heiko] Retrieval of ECID shall not be dependent on external clocks or other external digital inputs to the component other than those required to operate the test logic (tap ports including TCK, compliance-enable ports, etc.)
    • {Slide 28} Init-Data Register has a length that will depend on the chip design, but is potentially very long. Data loading may require PDL. Brad asked if bits can take different roles through multiple writes as happens with some PLDs. Heiko assumed the bits were dedicated, while Harrison thought Brad was probably right. Adam added that sequencing is allowed under PDL and that bit mapping was at the discretion of the chip designer.
    • [Heiko] When a simple power-up (explicit internal POR or TRST* signal) is inadequate for initializing a complex component for board test, then the initialization data register can be used to provide the information required to complete the initialization prior to the start of board or other testing. This is intended for programmable I/O in particular, but can be used for other characteristics of the component as well. Optionally, if some of the critical initialization parameters are supplied through input pins, then this register can monitor those pins so that their value is verified prior to starting interconnection tests.
      The initialization required will often vary from board to board, or from an instance on a board to another instance on the same board. It cannot be defined directly in the BSDL, since the BSDL documents the component design, not its use. BSDL now supports the naming of fields within a register, and provides named constants (mnemonics) for use with those fields. A new language (PDL) allows specification of the values to be loaded into, or expected from, specific instances of a component in a specific environment.
      These new capabilities should be used to initialize complex components for test. They are not intended to initialize the component for system operation.
      Dedicated to maintaining the initialization of the component, and in particular the component programmable I/O as long as the test logic is active;
    • {Slide 29} Init-Status Register is at least two bits long. Additional bits may be used to provide extended failure or status information.
    • [Heiko] Read-only register; required if INIT_RUN is implemented; If the initialization process is designed without a pass/fail indication, bit 1 shall always capture a logical 1;
    • {Slide 30} Reset-Select Register is at least three bits long. Each additional reset adds two more bits.
    • [Heiko] When the reset-hold update register stage is set to a logic '1', the reset-selection update register shall be initialized to the values enabling the reset source to control all of the system reset signals during the Test-Logic-Reset TAP controller state.
      When the reset-hold update register stage is set to a logic '0', the logic values of the reset-selection update register shall not change during the Test-Logic-Reset TAP controller state.
      Reset-enable bit:
      • 1 selects control of the system reset signal by system reset source (normally a reset pin, but could be an internally generated reset);
      • 0 selects control of the system reset signal by the reset-control bit;
      As the relationships between pairs of reset-control and reset-enable cells and individual reset sources and reset signals to the system logic are not defined by these rules, the reset-selection register shall be documented in BSDL using the REGISTER_FIELDS or REGISTER_ASSEMBLY attributes and, if the reset source is an input signal pin, the REGISTER_ ASSOCIATION attribute. To avoid problems related to race-conditions, the reset-enable bit(s) could be asserted in one scan to take control away from the reset source(s) prior to asserting and de-asserting the reset-control bit(s) in subsequent scans.
    • Due to the time, it was decided to break at that point. Heiko asked if it was worth presenting the remaining slides to the meeting or better to just circulate the slides for offline review. Ian and Brad both felt there was enough prospect of discussion to warrant keeping this on the agenda.
    • The slides from todays meeting are available on the SJTAG website: http://files.sjtag.org/Heiko/new%20in%20IEEE%201149-2012.pdf

5. Key Takeaway for today's meeting

  • Many of the new features are declared optional, while SJTAG seems to need more things, some of which are in the current standard, to be mandatory.

6. Schedule next meeting

Next Meeting:
July 2 - Carl and Ian are likely to be absent.

July schedule:
9, 16, 23, 30

7. Any other business


8. Review new action items


9. Adjourn

Eric moved to adjourn at 12:13 PM EDT, seconded by Brad.

Thanks to Heiko for his efforts in preparing the presentation for this week.

Respectfully submitted,
Ian McIntosh