Minutes of Weekly Meeting, 2013-12-09

Meeting called to order: 11:08 AM EST

1. Roll Call

Ian McIntosh
Peter Horwood (left 11:51)
Tim Pender
Adam Ley (left 12:03)
Brian Erickson
Brad Van Treuren (joined 11:17)

Patrick Au (for next three weeks)
Carl Walker
Heiko Ehrenberg
Eric Cormack

2. Review and approve previous minutes:


  • Draft circulated 11/18/2013.
  • Eric had previously noted two corrections, both near the end of 5a:
    • Now we are beginning to see BScan as an interface to other functions and features.
    • Ian thought that most of the other comments made by Adam were statements that required no further explanation.
  • Insufficient attendees to vote on approval.


  • Draft circulated 11/25/2013.
  • No corrections advised.
  • Insufficient attendees to vote on approval.


  • Draft circulated 12/02/2013.
  • No corrections advised.
  • Insufficient attendees to vote on approval.

3. Review old action items

  • All: do we feel SJTAG is requiring a new test language to obtain the information needed for diagnostics or is STAPL/SVF sufficient? See also Gunnar's presentation, in particular the new information he'd be looking for in a test language (http://files.sjtag.org/Ericsson-Nov2006/STAPL-Ideas.pdf)
  • Harrison will attempt to come up with a table of use cases and their associated layer and what can be done at that layer. Ongoing.
  • Ian/All: Look for real world examples of boards that we could take through from board test to a system test implementation as a worked example case. Ongoing.
  • Ian - Add the previously discussed lists to the 'master' template. Ongoing.
    • Some sections need further expansion that may take time to develop.

4. Reminders

  • Consider Adam's three points (from the action from the first weekly meeting) and suggest what is preventing us from answering those questions:
  • Establish consensus on goals and constraints
  • What are we trying to achieve?
  • What restrictions are we faced with?
  • Forum thread for discussion: http://forums.sjtag.org/viewtopic.php?f=3&t=172

5. Discussion Topics

a.  Report from BTW.

  • Ian gave a summary of the proceedings at BTW in Austin: The format was essentially an open, round table discussion on themes led out by Bill.  The format allowed the discussion to develop in whatever directions the room chose to go.  That seemed to be very productive and will likely be retained in some form at the next BTW, although there will generally be a return to the traditional submitted paper format.  BTW 2014 is expected to be in Austin again, possibly during 2nd week of September to avoid clashing with events such as Austin City Limits and the F1 Grand Prix.  Venue would likely be Cisco again or possibly Dell.  Notifications would be going out in late Spring.
  • The discussions were more productive that Bill had anticipated and of the 8 or so originally suggested topics only maybe 5 were addressed, and not always in the same form as originally suggested.
  • The first topic considered "Big Data".  There were comments on the volume of data that could be collected and its storage, and the importance of knowing what you needed the data for.  A key point for Ian was that it was important to know when a board assembler makes a process adjustment as that may explain step changes in observed data.  A lot of the discussion reflected things that Selex had been looking at in collecting build and test data for boards and mining it in the event of faults.
  • Possible confusion over the roles of 1149.1, 1500, P1687 was largely dismissed by the room, but it was acknowledged that 1500 was often misused by device designers (mainly memory devices) and that PDL existed in both 1149.1-2013 and P1687 but were not identical.  The opinion was voiced by some that if they're not the same thing they should be given different names.
  • Discussion on P1687 drifted onto security and Al Crouch described how SIBs could be used to provide nested accesses to registers that could act as key locations to unlock access to a devices TDR.  Ian hadn't had the opportunity to think this through yet, but at this point he was unconvinced that this technique it was as secure as presented.
  • Phil Geiger had presented material on iNEMI's activities and 5-year plan.  One thing that was in the pipeline was a follow-up to the BSDL survey of a couple of years ago; are BSDLs getting better, about the same or getting worse?  It was noted in discussion that as well as BSDLs we can expect to see CTL from 1500 and PDLs from 1149.1-2013 and P1687 and ICL from P1687.  It was suggested that a lot of people my get these additional files and have no idea what to do with them.
  • Brad asked if there was any discussion about FPGAs with instruments in IP which would mean needing BSDLs for configured devices as well as unconfigured parts.  Ian commented that there was very little mention of FPGAs at all and the discussion seemed to be more predicated on ASICs.
  • Adam added that Steve Butkovich and Phil Geiger were instrumental in the iNEMI Boundary Scan Phase 1 activity that led to the original survey.  That activity (ref JTAG at iNEMI) is now in Phase 3 and the new survey is being finalized and is expected out next year, however they'd probably welcome suggestions for areas to tackle in the survey.  Adam was monitoring the group and could take suggestions forward.
  • There was some discussion on 3D and the point had been made that 3D structures really needed to have their resources close at hand for efficiency.  Brad asked if dot7 was mentioned for 3D, since it seemed to be the best fit for that architecture.  Ian replied that it wasn't mentioned, but there had been suggestion that we might see things being tried out 2.5D first.
  • The SJTAG discussion was on the Thursday morning.  There was reasonable discussion around the definition of "a system" and Bill referred to Wikipedia (http://en.wikipedia.org/wiki/System):
    • A system has structure, it contains parts (or components) that are directly or indirectly related to each other;
    • A system has behavior, it contains processes that transform inputs into outputs (material, energy or data);
    • A system has interconnectivity: the parts and processes are connected by structural and/or behavioral relationships.
    • A system's structure and behavior may be decomposed via subsystems and sub-processes to elementary parts and process steps.
  •  In discussing the templates, Al Crouch drew comparisons with the BA-BIST templates.  Ian noted that the BA-BIST template used the term "Goal" which was roughly equivalent to our "Operation Overview Being Analyzed".  Brad commented that BA-BIST was looking at the Right Hand Side (the chip level) of Al's diagram while SJTAG could be looking and the Left Hand Side (the board/system level).
  • There was broad agreement on the value of not constraining SJTAG to 1149.1.  Brad noted that SPI and I2C would run out of capacity as instrument densities increase, and replied that it further strengthened the argument that SJTAG needs to future proof itself by being agnostic of the interfaces in use.
  • Bill Eklow was strongly urging SJTAG to get a PAR submitted, even loosely defined.  Ian was now appreciating that there was little problem in having a scope that allowed more than the standard eventually addresses; the problem arise when the scope is too narrow and the standard tries to address more.  Adam added that it was perfectly acceptable to revise the scope and purpose of the PAR during its lifetime.  One or two changes would not be considered excessive, should the definitions be found to be wanting.
  • {The following additional notes were provided by Heiko as proxy}


    • Ian presented on SJTAG
    • Bill: maybe a good starting point would be a standardized description of what the system looks like, in a block level architecture kind of way;
    • Al: iNemi did a similar thing (with templates); we actually included in the template a statement of what constitutes a Fail;
    • Bill: neither 1149.1 nor P1687 have a concept of managing two instruments to work together; this could be SJTAG's first / initial task;
    • Bill: recommends to file a PAR for a simple first step at a high level (e.g. system architecture description);


  • Ian commented that as a result of how the discussions were moving during the Wednesday, he had added two slides from the 2008 ITC pack to show the conventional JTAG "universe" and the "SJTAG Universe".  The final pack, as presented, is on the website on the Stored Documents page. 
  • The final discussion was on what a Test Engineer will look like in 5 or 10 years time.  There was a general concern that many firms are not recruiting new Test Engineers, and the current breed are moving on.  Absence of training at college level and incentives to attract new engineers to Test Engineering were discussed as well growing new Test Engineers from Technicians.

6. Key Takeaway for today's meeting

  • None.

7. Schedule next meeting

  • Next Meeting: December 16 - Brad, Carl, Peter absent.
  • January schedule:
    6, 13, 20, 27

8. Any other business

  • Brad asked if there had been any resolution to the meeting time conflict with 1149.10.  Ian advised that there was little we could do about it as the survey on alternate times showed that all the other possible times were inconvenient to at least one other person, meaning we'd lose as many people as we'd gain from any change.  The only thought was whether people might find their schedules changing in the New Year, or if sufficient people were involved with dot10 and requested a reschedule.

9. Review new action items

  • None.

10. Adjourn

Brian moved to adjourn at 12:17 PM EST, seconded by Brad.

Respectfully submitted, Ian McIntosh