Minutes of Weekly Meeting, 2015-08-03

Meeting called to order: 11:06 AM EDT

1. Roll Call

Ian McIntosh
Carl Walker
Brian Erickson
Eric Cormack
Peter Horwood
Brad Van Treuren
Michele Portolan
Tim Pender
Bill Eklow (joined 11:21)

Adam Ley
Heiko Ehrenberg

2. Review and approve previous minutes:

  • Approval of July 27 minutes (draft circulated 7/27/2015):
    • No corrections noted.
    • Brad moved to approve, seconded by Eric, no objections or abstentions.

3. Review old action items

  • All: do we feel SJTAG is requiring a new test language to obtain the information needed for diagnostics or is STAPL/SVF sufficient? See also Gunnar's presentation, in particular the new information he'd be looking for in a test language (http://files.sjtag.org/Ericsson-Nov2006/STAPL-Ideas.pdf)
  • Ian: Add the previously discussed lists to the 'master' template. Ongoing.
    • Some sections need further expansion that may take time to develop.

4. Reminders

  • Consider Adam's three points (from the action from the first weekly meeting) and suggest what is preventing us from answering those questions:
    • Establish consensus on goals and constraints
    • What are we trying to achieve?
    • What restrictions are we faced with?
  • Forum thread for discussion: http://forums.sjtag.org/viewtopic.php?f=3&t=172

5. Discussion Topics

a. ITC Participation.

  • Michele has an offer to present a poster that he could forfeit to support an SJTAG one.  This probably unnecessary as Heiko had offered to man our poster as he has a colleague who could cover the poster that Heiko was expecting to present.
  • It would be advantageous if Michele's poster was located close to the SJTAG one to make the connection more apparent.
  • A panel had been discussed previously.  Ian felt it would be too hard to get an appropriate panel membership, while Brad and Michele agreed that there may not be enough audience feedback to be a valuable session.
  • ITC is the first week of October, so there's not a lot of time to prepare material. Michele intends that his poster will mainly be about his execution engine; that should tie in with SJTAG, going from one specific example to the general approach.
  • Brad though the SJTAG poster should show the control and co-ordination of access links and data links - this would be complementary to Michele's poster.
  • {The following was added after Bill had joined the call}
  • Michele is nominally listed for an invited talk in section headed "Boundary Scan to the Rescue". This probably gives us more scope for supporting a poster and promoting the connection to SJTAG.

b. Try to identify pictorially what we mean by our Scan Operation (continuation).

  • {Shared AccessLink Postcondition (without NOP states)}.
  • Brad: Probably don't need separate notation to indicate 0-or-more or 1-or-more: To add the "or more" it just needs the bubble to show a loop to itself, while the 0 or 1 is indicated by whether or not a bubble is bypassed.
  • Tim: The Select/Disconnect seems to be dealing with chains; what about when the downstream chain also contains a bus? It can't really be connected at the same time as the rest of the chain.
  • {There was some confusion over exactly what architecture was being described at this point}
  • Peter: I think Tim means where a chain has another gateway in it - tools have often failed to handle that properly.
  • Brad: I think it's not quite that, maybe a hybrid.
  • Tim: You may want chains on the secondary, but in a rack also want to have busses to ASPs, while having single point access.
  • Brad: If you mean were something in the chain is acting as the bus controller, then that's probably not easily controllable, but you can deal with it as a bridge, though you'll need to write the bus controller.
  • Tim: Suppose you have two busses: You can't do any broadcasts to both simultaneously as the TDOs will mess up.
  • Peter: We handle that: In Broadcast, the TDOs get turned off, so you can do things like gang programming. If you want to access cards of the same type you put them in the same multicast group.
  • Tim: I mean both connected in the secondary, not really a hybrid.
  • Brad: I think that's no different to a bridge. Still need to perform certain steps.
  • Tim: I'm seeing the selector as the primary method of chain selection, but we have two different systems.
  • Brad: There's the AccessLink Connect, which is representative of addressing an ASP, and AccessLink Select which is more like the LASP port selection, although in the LASP the Connect and Select both happen in the one step. 
  • Brad: We're getting into the multiplicity of access links here.  These diagrams are more about what modes the hardware goes through. Something has to provide the connection to the bus but then you still need to select the slave.
  • Tim: I see that as coming from the host.
  • Brad: Something in the model needs to tell the host what to send out to get the expected response.
  • Brad: This is another Use Case needed in our assessment.
  • {Shared AccessLink Cycle}
  • This is the only diagram that needs to show iterations, however it is missing the bypasses of the Precondition and Postcondition bubbles.
  • Ian wondered if the Access_Data_Transfer bubbles was singular or could happen multiple times: The preconditioning could occur then several data transfers before applying the post condition or every transfer could be wrapped with preconditioning and post conditioning. It becomes a question of efficiency and probably a choice for tooling. Brad noted that the bypasses would allow the entire cycle to be repeated without adding unnecessary actions.
  • Ian: The only change we need to diagrams appears to be to add bypasses to this one?
  • Brad: Agreed.
  • Ian: For next week, is it better to look at the Data Transfer or the activities with Preconditioning/Postconditioning?
  • Brad: A question I have over the Data Transfer is are we just representing the Data Register or also how we write to the Data Register. In 1687, all the registers are the same, but they could be very different in our case.
  • Brad: Does the write method get handled by the Preconditioning and the data just arrives at the Data Register?
  • Ian: Perhaps that means we need to look at the preconditioning first, as it may answer the question for us.
  • Brad: We're trying to make all Data Register appear the same to an SJTAG operation; how it gets addressed and data put there should be hidden from the user.
  • Brad: A memory mapped instrument may be accessed from a JTAG AXI controller or through a debug mode or embedded application (where it really is memory mapped).  In each case it is the same data.  The tools need to figure out what needs to be done.

c. Start defining what activities need to be done during pre-conditioning.

  • {Not discussed}

6. Topic for next meeting

  • Start defining what activities need to be done during pre-conditioning.

7. Key Takeaway for today's meeting

  • Multiplicity can be described by additional "edges" on the existing diagram.

8. Glossary terms from this meeting

  • None.

9. Schedule next meeting

  • August 10 - Peter out for the next three weeks
  • August schedule: 10, 17, 24, 31: Eric out 24 and 31.

10. Any other business

  • The Newsletter was due at the end of July.

11. Review new action items

  • None.

12. Adjourn

  • Eric moved to adjourn, seconded by Tim.
  • Meeting adjourned at 11:59 AM EDT

Respectfully submitted,
Ian McIntosh