Minutes of Study Group Meeting, 2017-08-28

Meeting called to order: 11:08 AM EDT

The slide references relate to the packs used during this meeting and located:
IM1: http://files.sjtag.org/StudyGroup/SG_Meeting_3.pdf
JR: http://files.sjtag.org/StudyGroup/SJTAG_P1687.1_interop_20170828.pdf
IM2: http://files.sjtag.org/StudyGroup/System%20Examples_v4.pdf

1. Roll Call

Ian McIntosh (Leonardo MW Ltd.)
Heiko Ehrenberg (Goepel Electronics)
Brad Van Treuren (Nokia)
Eric Cormack (DFT Solutions Ltd.)
Brian Erickson (JTAG Technologies)
Carl Walker (Cisco Systems)
Adam Ley (ASSET Intertech)
Brent Bullock (Advantest)
Bill Huynh (Marvell Inc.)
Joel Irby (ARM)
Martin Keim (Mentor Graphics)
Rajesh Khurana (Cadence Design Systems)
Roger Lin (Via CPU Platform Inc.)
Teresa McLaurin (ARM)
Mukund Modi (Navy Lakehurst)
Prasanth Pillai (Texas Instruments)
Richard Pistor (Curtiss-Wright)
Naveen Srivastrava (Nvidia)
Jon Stewart) (Dell)
Jeff Rearick (AMD) (Invited Presenter)

By email (non-attendees):

Peter Horwood (Firecron Ltd.)

2. IEEE Patent Slides

  • {IM1, Slides 5-9}

3. Review and Approve Previous Minutes

  • {IM1, Slide 10}
  • August 21
    • Draft circulated 8/21/17
    • No corrections
    • Eric moved to approve, seconded by Brad, no objections or abstentions. Approved.

4. Review Open Action Items

  • {IM1, Slide 11}
  • [2.1] Bill: Ask Al Crouch about sharing the 1687.1 poster abstract with the group
    • Bill was not on the call, no update available. Continues.

5. Discussion Topics

a) ITC Poster

  • {IM1, Slide 12}
  • No discussion.

b) 1687.1 perspective of SJTAG

  • {IM1, slide 13}
  • Presentation led by Jeff Rearick {JR, Slides 2-10}
    • 1687 serial access model with TAP.
    • How does 1687.1 translate to a non-TAP device boundary?
    • Memory mapped register (portal, addressable Data Register) with TransformationEngine. Addressable Data Register has an associated callback. Intent conveyed through extended ICL: iNOTE with Payload - allows linking a reported failure with an action.
    • Memory mapped instruments (functional registers) described by PDL. 
    • Concept of a clean boundary between 1687.1 and SJTAG at the device boundary.
    • Board example, green devices work well with 1687.
    • Overlay with notional retargeting domains.
    • What differentiates 1687.1 and SJTAG if there is no firm boundary?
    • Callback proposals: SJTAG (notional), Jeff's, Michele's.
    • Breakout to some slides extracted from a pack by Michele Portolan showing how everything could be handled as a chain of call backs.
  • {JR, Slide 8}
  • SJTAG probably needs to overlay the 1149.1 zone at the left side. Suggests SJTAG may not be a contiguous domain. SJTAG might have a clean handover to some standards but overlay on top of others.
  • SJTAG expects to leverage other standards but they are not defined with consistent/coherent interfaces.
  • How would a hierarchy of callbacks be defined?
  • Could ICL define a board?
    • Probably, but board design is unlikely to have the resource or budget to prepare appropriate documentation that chip design would. No equivalent to the chip "Integrator".
  • {IM2, Slide 7}
  • SJTAG board example. Show similarities with Jeff's slides 7/8. Does not capture prospect of the bridge devices providing 1687 access to downstream host controllers.
  • There is overlap in the aims of 1687.1  and SJTAG but while 1687 and 1687.1 seem to be more focussed on providing access to the instruments, SJTAG is looking to manage what happens and when - sequencing events and setup of conditions.
  • Chip designers cannot reasonably predict the intent of board level tests, nor what other devices a given chip may require to interoperate with in the execution of a test. Could only list what test functions are available to the board test designer.
  • Tools for BScan might typically offer an interconnect test or Flash programming algorithms - different intents on the same hardware model.
  • MBIST test blocks may need to be sequenced in order to manage power consumption.
  • Conditional execution is not available in PDL level-0 but could be handled by PDL level-1.
  • A SERDES test may involve a serializer in one device defined by 1687 and a de-serializer in another device defined by 1149.1-2013 - similar but not the same and SJTAG would provide the bridges.
  • Come back to this topic in three or four weeks once the respective groups have had a chance to consider this discussion.

6. Today's Key Takeaways

  • {IM1, Slide 14}
  • Demarcation between 1687.1 and SJTAG will be addressed through perspective and intent.

7. Glossary Terms from This Meeting

  • None.

8. Topic for next meeting

  • Study Group objectives - things we need to report for TTSC.

9. Schedule next meeting

  • September 11.
    • September 4 will be Labor Day - probably no quorum.

10. Reminders

  • None.

11. Any Other Business

  • None.

12. List New Action Items

  • None.

13. Adjourn

  • Brad moved to adjourn, seconded by Naveen.
  • Meeting adjourned at 12:19 PM EDT

Thanks to Jeff Rearick for joining today's call.

Respectfully submitted,
Ian McIntosh