|An SJTAG Architectural Concept
(A description of SJTAG Green Papers can be found
Looking at an entire system to understand the complexity of control and
test operations is a daunting task. Decomposing the problem into smaller pieces
does not always provide insights unless one is able to discover commonalities
between these levels. A key insight for SJTAG is the realization that the lowest
common denominator for all test and control points in the problem domain is the
basic Test Data Register (TDR). This primitive follows the basic constraint
supporting a serial shift protocol implementing a Capture-Shift-Update (CSU)
strategy as defined by the IEEE 1149.1 TAP state machine. Important discoveries
is that other control protocols used for system test and configuration (e.g.,
I2C, SPI, memory mapped) are able to support this same CSU protocol either
directly or indirectly using these other interfaces. How the data is passed
through a communication channel down to a TDR is controlled by the AccessLink
defining the control aspect of the data and the DataLink that is responsible
for transporting the data through that AccessLink. These concepts for the system
and board domains are described in this Green Paper.
It has been almost ten years since the IEEE System
JTAG study group was formed. In that time there have been
many new standards created that have one thing in common – they are rooted in
IEEE 1149.1. It has not been a clear journey as many of these standards looked
more like a moving target for how they can be used at the board and system level.
It wasn’t until the advent of the IEEE 1149.1-2013 release and the IEEE P1687
draft that the concept of decoupling the structure of the Test Data Register
(TDR) from the access mechanism that is used to communicate with the TDR became
an important cohesive concept. Each of the inheriting standards incorporates
the use of a TDR to communicate with the special features they represent.
Figure 1 - Illustrative SJTAG System
Thus, the common feature for all of these standards is the TDR; contrary to
the idea that these are standardized on the JTAG TAP Controller. The TDR is
based on the protocol established by the TAP State Machine as defined by the
1149.1 standard. This protocol defines the Capture-Shift-Update timing and
scan order of the information in a standardized format equivalent to a data
communications protocol physical layer. This serial scan protocol defines how
the data gets sent and received inside the chip – the Data Link. As long as
the data format and structure adheres to the protocol defined for the TDR, it
is not critical to understand where and how that data arrives to the internal
structure of the device. With that said, one can abstract out the concept of
the access mechanism used to transport the data through the board and system
to the TDR. This abstraction allows for the decoupling of the transported data
from the access mechanism used to transport that data. The concept of the
access mechanism is also known as the Access Link or Access Interface for a
device. Defining the Data Link and Access Link is not the only thing required
for use at the board and system level of a design. There also needs to exist a
controlling infrastructure to manage and coordinate the multitude of device
instrumentation found throughout a system as well as the relationship for how
these instruments are connected together – the structure of the scan network.
To help understand what a System Under Test represents, a theoretical model of
a typical system is depicted in Figure 1.
Figures 2, 3 and 4
To read the rest of this article please follow the link below.
Main article link: http://www.sjtag.org/index.php/news/305-an-sjtag-architectural-concept
From the Chair
Some of our Group attended the Board Test Workshop in Austin during December where we gave
a brief presentation around the Templates we described in our last newsletter, which prompted some good discussion and
significant interest. The follow-up activity has led to some consolidation of our views and the main article presented
in this newsletter.
Although we cannot confirm it at this juncture, we are anticipating that we may have a further presentation to offer
at the European Test Symposium in May 2014, in the
ETS Special Track on Emerging Test Strategies.
We'll keep you informed through the newsletter and our website.
ETS '14 Website: http://www.ets14.de/
SJTAG Website: http://www.sjtag.org/
The group voted in February to reaffirm both Ian McIntosh and Heiko Ehrenberg in the roles of
Chair and Vice Chair respectively for 2014.
News post: Group Officers for 2014
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